Re: [libre-riscv-dev] Finished Scoreboard

Re: [libre-riscv-dev] Finished Scoreboard

[Luke Kenneth Casson Leighton]

On Tue, May 5, 2020 at 5:15 PM Yehowshua <yimmanuel3@gatech.edu> wrote:
>
> Do you think the scoreboard can be done by mid June?

i'm assuming you meant to ask this on the list.

the actual scoreboard (dependency matrices) themselves are "done".  it
was only the change to multi-signal control at the register file that
needed alteration, and *that* was done several weeks ago (didn't take
long).

it's the "arbitration" connectivity to the register file (3 days
design work on the cyclic buffer system), the LDSTCompUnit (10 days
redesign, 2-3 days implementing, the change to the ALU CompUnit (8
days redesign, 2-3 days implementing) that is the time-sink.

the next phase is to create a POWER9 "Condition" Register File
containing CR0-CR7, CTR and other essential registers related to
Branch Control.  this *extra register file* was the primary motivation
behind the additional scoreboard read/write "operand" wires, because
one set manages the INT/FP regfile, another set manages the "Condition
Register" regfile (oh, and another set - with a completely different
DM Matrix - manages the SPRs.

which is why we need people to focus on "ancillary" tasks because
without people focussing on ancillary tasks, we're not going to have
instructions completed, the pipelines designed, the memory interface
completed, no Branch Prediction Unit, no TLB, no RADIX MMU.

hence the urgency of asking people to focus on specific tasks, and not
anything else.

the amount that we have to do in such a short amount of time is
enormous, and we need to bash through it, without wasting *any* time.

l.

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Re: [libre-riscv-dev] Finished Scoreboard

[Yehowshua]

Well I’d like to be realistic. I’ve done large RTL projects before - if the scoreboard isn’t ready to do by June, we may have to look into the minimum viable product for October. Having a multi cycle non-pipelined CPU is way better than no CPU.

Luke, given only you have the knowledge to do the Scoreboard at the moment, it’d be wise to put eggs in more than one basket. Also, it takes at least a semester to fully comprehend the scoreboard architecture, so we can’t just add people to help you.

Just some things to keep in mind.

Yehowshua
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Re: [libre-riscv-dev] Finished Scoreboard

[Immanuel, Yehowshua U]

Maybe we could say finished by Mid-June - but more than that would really be pushing things I think.

Yehowshua
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Re: [libre-riscv-dev] Finished Scoreboard

[Luke Kenneth Casson Leighton]

On Tuesday, May 5, 2020, Immanuel, Yehowshua U <yimmanuel3@gatech.edu>
wrote:

> Maybe we could say finished by Mid-June -


yes.


>
>  but more than that would really be pushing things I think.


yes.




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Re: [libre-riscv-dev] Finished Scoreboard

[Luke Kenneth Casson Leighton]

On Tuesday, May 5, 2020, Yehowshua <yimmanuel3@gatech.edu> wrote:

> Well I’d like to be realistic. I’ve done large RTL projects before - if
> the scoreboard isn’t ready to do by June, we may have to look into the
> minimum viable product for October. Having a multi cycle non-pipelined CPU
> is way better than no CPU.


 NLNet money is only available for the defined set task.  No GPU, no money.

that means that alternative designs will need to find other sources of
funds.


> Luke, given only you have the knowledge to do the Scoreboard at the
> moment, it’d be wise to put eggs in more than one basket. Also, it takes at
> least a semester to fully comprehend the scoreboard architecture, so we
> can’t just add people to help you.


ancillary tasks.

>
> Just some things to keep in mind.
>
> Yehowshua
> _______________________________________________
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> libre-riscv-dev@lists.libre-riscv.org
> http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev
>


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