[libre-riscv-dev] daily kan-ban update 11jun2020

[libre-riscv-dev] daily kan-ban update 11jun2020

[Luke Kenneth Casson Leighton]

today:

dealing with yet more complexity in CompALUMulti and investigating ST
followed by LD issues in LDSTCompUnit

l.



-- 
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev

Re: [libre-riscv-dev] daily kan-ban update 11jun2020

[Tobias Platen]

today: reading src/soc/scoreboard/addr_split.py and thinking how to imlement memory interface
tomorrow: nothing (I won't be at home tomorrow)

-- 
Tobias Platen <libre-soc[at]platen-software[dot]de>

_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev

Re: [libre-riscv-dev] daily kan-ban update 11jun2020

[Luke Kenneth Casson Leighton]

On Thursday, June 11, 2020, Tobias Platen <libre-soc@platen-software.de>
wrote:

> today: reading src/soc/scoreboard/addr_split.py and thinking how to
> imlement memory interface


look up what i wrote yesterday, i recommended expanding the existing
LDSTSplitter from bits to bytes.

it was accidental that it did bits of data :)



> tomorrow: nothing (I won't be at home tomorrow)
>
> --
> Tobias Platen <libre-soc[at]platen-software[dot]de>
>
> _______________________________________________
> libre-riscv-dev mailing list
> libre-riscv-dev@lists.libre-riscv.org
> http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev
>


-- 
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev

Re: [libre-riscv-dev] daily kan-ban update 11jun2020

[Jacob Lifshay]

today:
wrote up a short status report on Kazan
working on div and mul pipelines
attending OpenPower virtual coffee meeting

Jacob
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev

Re: [libre-riscv-dev] daily kan-ban update 11jun2020

[Cesar Strauss]

Ongoing:

* Work on the parallel test concept in
src/soc/experiment/test/test_compalu_multi.py.

Recently:

* Implement proper ready / valid signaling on the test ALU at
src/soc/experiment/alu_hier.py

Today:

* Looking into compldst_multi.py's unit tests to confirm that they are
properly functional
* (off-project): git bisecting systemd due to getting system freezes
after an upgrade. Fun.

Interesting tools and readings, to share:

* Pipelined Skid Buffer

http://fpgacpu.ca/fpga/Pipeline_Skid_Buffer.html

The circuit itself is useful, for meeting timing on long pipelines. But,
specially, I find it a nice example of the Finite State Machine (FSM)
technique, from requirements, concept and diagram, to design and
implementation. Doesn't cover unit tests and formal proofs, though.

* GTKWave package, from the PyVCD module

https://pyvcd.readthedocs.io/en/latest/vcd.gtkw.html

While used in a limited way by nMigen itself, for pre-filling traces in
a GTKWave window, it can do much more: comments, blank separators, trace
colors, scale, etc.

* Synchronous Resets? Asynchronous Resets? I am so confused! How will I
ever know which to use? by Clifford E. Cummings

http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf

* Clock Domain Crossing (CDC) Design & Verification Techniques Using
SystemVerilog, by Clifford E. Cummings

http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf

In particular, see section 5.8.2: Multi-bit CDC signal passing using
1-deep / 2-register FIFO synchronizer.

* Understanding Latency Hiding on GPUs, by Vasily Volkov

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-143.pdf

Nice introductory chapter on internal GPU architecture.

Regards,

Cesar

_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev

Re: [libre-riscv-dev] daily kan-ban update 11jun2020

[Luke Kenneth Casson Leighton]

On Thu, Jun 11, 2020 at 10:02 PM Cesar Strauss <cestrauss@gmail.com> wrote:

> Interesting tools and readings, to share:

i liked them, i added them to the "other" section on the resources page.
feel free to do that in future, it's what the Documentation Website
(wiki) is for.
https://libre-soc.org/resources/#index16h1

l.

_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev

Re: [libre-riscv-dev] daily kan-ban update 11jun2020

[Cole Poirier]

On Jun 11 2020, at 2:02 pm, Cesar Strauss <cestrauss@gmail.com> wrote:
> Interesting tools and readings, to share:
> 
> * Pipelined Skid Buffer
> 
> http://fpgacpu.ca/fpga/Pipeline_Skid_Buffer.html
 [snip]
> * Understanding Latency Hiding on GPUs, by Vasily Volkov
> 
> http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-143.pdf
> 
> Nice introductory chapter on internal GPU architecture.

Thanks so much for sharing these resources Cesar! I skimmed them
yesterday and I think they'll be really useful for me to understand some
of these complex computer architecture concepts.

Cole

_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev