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From: Jacob Lifshay <programmerjake@gmail.com>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] daily kan-ban update, 22jul2020
Date: Wed, 22 Jul 2020 17:13:47 -0700
Message-ID: <CAC2bXD5AfjdHnHQ4JVh43MDzM-T=FCdCrbtUYVwHecDLUN1ZiQ@mail.gmail.com> (raw)

today:
still working on Div FSM -- I think it's complete (except for not
supporting cancellation), but didn't thoroughly test it yet. In the
process of refactoring test_pipe_caller.py into a easier-to-test shape
and adding parallel test cases for DivPipeCore, FSMDivCore, and
SimOnly, I discovered that for test_divwuo_regression_1 (0xc4e32b68 /
0x32867d69), the pipeline (SimOnly) is giving the correct results
(rt=0x3), it's the ISA simulator code that's messed up
(rt=0xFFFFFFFF).

Luke (or whoever is more familiar with it), I'll let you figure out
how to fix the ISA simulator.

Jacob

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Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-23  0:13 Jacob Lifshay [this message]
2020-07-23  1:53 ` Cole Poirier
2020-07-23  2:29 ` Luke Kenneth Casson Leighton
2020-07-23  9:40   ` Luke Kenneth Casson Leighton
2020-07-23 16:31     ` Jacob Lifshay
2020-07-23 16:42       ` Luke Kenneth Casson Leighton
2020-07-23 17:06         ` Jacob Lifshay
2020-07-23 17:11           ` Luke Kenneth Casson Leighton

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