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From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] daily kan-ban update, 22jul2020
Date: Thu, 23 Jul 2020 03:29:47 +0100
Message-ID: <CAPweEDwNs=hhEWEL0LKi23BORTLhGRUFwH=CXOXtcH6tdNJLGQ@mail.gmail.com> (raw)
In-Reply-To: <CAC2bXD5AfjdHnHQ4JVh43MDzM-T=FCdCrbtUYVwHecDLUN1ZiQ@mail.gmail.com>

On Thursday, July 23, 2020, Jacob Lifshay <programmerjake@gmail.com> wrote:

> today:
> still working on Div FSM -- I think it's complete (except for not
> supporting cancellation), but didn't thoroughly test it yet. In the
> process of refactoring test_pipe_caller.py into a easier-to-test shape
> and adding parallel test cases for DivPipeCore, FSMDivCore, and
> SimOnly, I discovered that for test_divwuo_regression_1 (0xc4e32b68 /
> 0x32867d69), the pipeline (SimOnly) is giving the correct results
> (rt=0x3), it's the ISA simulator code that's messed up
> (rt=0xFFFFFFFF).


please raise a bugreport for it.


>
> Luke (or whoever is more familiar with it), I'll let you figure out
> how to fix the ISA simulator.


it's running the pseudocode.  if the pseudocode gives the wrong answer,
that's bad.

what happens when testing the same values in simulator/test_div_dim.py?

hm wait you can't put initial regs into qemu yet.  been meaning to add that.

l.



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Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-23  0:13 Jacob Lifshay
2020-07-23  1:53 ` Cole Poirier
2020-07-23  2:29 ` Luke Kenneth Casson Leighton [this message]
2020-07-23  9:40   ` Luke Kenneth Casson Leighton
2020-07-23 16:31     ` Jacob Lifshay
2020-07-23 16:42       ` Luke Kenneth Casson Leighton
2020-07-23 17:06         ` Jacob Lifshay
2020-07-23 17:11           ` Luke Kenneth Casson Leighton

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