Re: [libre-riscv-dev] div pipe

[Jacob Lifshay <programmerjake@gmail.com>]

On Sun, Jul 19, 2020, 18:39 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
wrote:

> On Monday, July 20, 2020, Jacob Lifshay <programmerjake@gmail.com> wrote:
>
> >
> > effectively what's happening is the code is treating the compare_?hs
> > signals as if the binary value N means the fraction N/2^(3*fract_width)
> > (essentially fixed-point numbers), so changing the bit width of N without
> > adjusting the fract_width means there are too few integer bits and too
> many
> > fractional bits.
>
>
> ahh i remember.  that took a while to get right when connecting to fpdiv.
>
>
> > additionally, some of the shifts and bit sliced will have
> > to be adjusted to get the right bits.
> >
> > >
> > > no reversion should be needed.
> > >
> >
> > except that, last I checked DivPipeCore doesn't correctly do divisions
> when
> > configured to only support UDivRem, since that's when it enables the
> broken
> > code adjustments.
>
>
> yuk.  hmm a way to "cheat" there: tell it that it can handle sqrt as well,
> temporarily :)
>

I think a better way would be to find all the code like:

if core_config.supported == {DP.UDivRem}:
    self.compare_len = bw * 2
else:
    self.compare_len = bw * 3

and replace every occurrence with:

# TODO(programmerjake): re-enable once bit_width reduction is fixed
if False and core_config.supported == {DP.UDivRem}:
    self.compare_len = bw * 2
else:
    self.compare_len = bw * 3

As far as I can tell, that should work.

Jacob
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