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From: Jacob Lifshay <programmerjake@gmail.com>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] div pipe
Date: Sun, 19 Jul 2020 20:21:57 -0700
Message-ID: <CAC2bXD5YA2_+xH_=zPUV-tcdTjAvF-QJa=cYQPCvYA75BvToEA@mail.gmail.com> (raw)
In-Reply-To: <CAPweEDyK8ms7jXbby1=JejzkjcKevb8ueDrs6naMipeR_119_A@mail.gmail.com>

On Sun, Jul 19, 2020 at 7:14 PM Luke Kenneth Casson Leighton
<lkcl@lkcl.net> wrote:
>
> On Monday, July 20, 2020, Jacob Lifshay <programmerjake@gmail.com> wrote:
>
> > l
> > and replace every occurrence with:
> >
> > # TODO(programmerjake): re-enable once bit_width reduction is fixed
>
>
> yeh that makes sense.
>
>
> > if False and core_config.supported == {DP.UDivRem}:
> >     self.
>
>
>
> > As far as I can tell, that should work

Pushed a fix.

Fixed the comb tests since the generate process was 1us ahead of the
check process, causing test failures.

Jacob

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Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-18 22:18 [libre-riscv-dev] lots of stuff broken Luke Kenneth Casson Leighton
2020-07-19  6:55 ` Jacob Lifshay
2020-07-19 10:46   ` Luke Kenneth Casson Leighton
2020-07-19 21:11     ` Luke Kenneth Casson Leighton
2020-07-19 21:27       ` [libre-riscv-dev] div pipe Jacob Lifshay
2020-07-19 22:07         ` Luke Kenneth Casson Leighton
2020-07-20  0:32           ` Jacob Lifshay
2020-07-20  1:38             ` Luke Kenneth Casson Leighton
2020-07-20  2:06               ` Jacob Lifshay
2020-07-20  2:13                 ` Luke Kenneth Casson Leighton
2020-07-20  3:21                   ` Jacob Lifshay [this message]
2020-07-20 10:31                     ` Luke Kenneth Casson Leighton

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