From: Jacob Lifshay <programmerjake@gmail.com>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog
Date: Wed, 13 May 2020 12:02:41 -0700
Message-ID: <CAC2bXD5P2P27+rfxq7v=zvtiTjHQJq5j5p3zED=3fhhG54vpHw@mail.gmail.com> (raw)
In-Reply-To: <48c106bb-90f0-3d67-6021-a9e1c2190faa@gmail.com>
On Wed, May 13, 2020, 11:52 Michael Nolan <mtnolan2640@gmail.com> wrote:
> On 5/13/20 2:18 PM, Luke Kenneth Casson Leighton wrote:
> > that's the simple version (and a cool one), i was thinking in terms of a
> > suite of single-bit full adders that then need to be manually linked up.
> >
> > in verilog or vhdl this is a total pain.
> >
> I agree it's easier to do in nmigen, but both verilog and vhdl support
> generate statements for doing just that.
>
Maybe a better (though maybe not realistic) example is trying to xor all
input bits where the bits' indexes are prime numbers, that would be
relatively easy in nmigen but quite hard in VHDL or Verilog.
Jacob
>
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Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-12 10:45 [libre-riscv-dev] daily kan-ban update 12may2020 Luke Kenneth Casson Leighton
2020-05-12 14:00 ` Tobias Platen
2020-05-12 14:28 ` Michael Nolan
2020-05-12 14:53 ` Luke Kenneth Casson Leighton
2020-05-12 14:42 ` Yehowshua
2020-05-12 15:03 ` Luke Kenneth Casson Leighton
2020-05-13 17:49 ` [libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog Jacob Lifshay
2020-05-13 18:18 ` Luke Kenneth Casson Leighton
2020-05-13 18:51 ` Michael Nolan
2020-05-13 19:02 ` Jacob Lifshay [this message]
2020-05-13 19:54 ` Luke Kenneth Casson Leighton
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