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From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] daily kan-ban update 12may2020
Date: Tue, 12 May 2020 15:53:34 +0100
Message-ID: <CAPweEDym6-2cwj8L53gM2ykotHA_qH_uaTMEYDJsWgrcMewRsQ@mail.gmail.com> (raw)
In-Reply-To: <dafc0660-613f-d9d4-ee5c-2f3ab0bb7475@gmail.com>

On Tue, May 12, 2020 at 3:29 PM Michael Nolan <mtnolan2640@gmail.com> wrote:
>
> Yesterday I modified the ALU tests to read the alu inputs as specified
> in the instruction instead of hardcoded register numbers.

great.  i think we also worked out, it's kinda been a long-standing
convention that, instead of adding yet another 64 bit data path to
feed the ALU, the RB wires are used to feed in the immediate.

otherwise you have 64 wires for RA, 64 wires for RB, 64 wires for
RC/RS, and *another* 64 wires for an immediate.

so this is why i think you see the 6600, and RISC-V, and Power, and
many others, all never doing a 2nd reg (RB) *and* an immediate.
there's a *third* register - RC - in the case of POWER, because unlike
RISC-V which seems to be based around 2-64-bit-inputs (except FMAC),
and 1-64-bit-output, POWER seems to be based around a much more
complex 3-64-bit-datapaths-in and up to *two* 64-bit-datapaths-out....
*plus* Condition Registers in and out.

> I refactored
> the test to greatly reduce the amount of time it takes to run (went from
> ~1m to ~3s on my computer)
>
> Today I'd like to split out the shift and rotate instructions into their
> own separate FU

i think that will help make things clearer, and the actual ALU code in
each module a lot shorter.

l.

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Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-12 10:45 Luke Kenneth Casson Leighton
2020-05-12 14:00 ` Tobias Platen
2020-05-12 14:28 ` Michael Nolan
2020-05-12 14:53   ` Luke Kenneth Casson Leighton [this message]
2020-05-12 14:42 ` Yehowshua
2020-05-12 15:03   ` Luke Kenneth Casson Leighton
2020-05-13 17:49     ` [libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog Jacob Lifshay
2020-05-13 18:18       ` Luke Kenneth Casson Leighton
2020-05-13 18:51         ` Michael Nolan
2020-05-13 19:02           ` Jacob Lifshay
2020-05-13 19:54           ` Luke Kenneth Casson Leighton

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