* [libre-riscv-dev] daily kan-ban update 12jul2020
@ 2020-07-12 12:43 Luke Kenneth Casson Leighton
2020-07-13 1:48 ` Jacob Lifshay
0 siblings, 1 reply; 6+ messages in thread
From: Luke Kenneth Casson Leighton @ 2020-07-12 12:43 UTC (permalink / raw)
To: Libre-RISCV General Development
tasks:
https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1
yesterday:
* big addition of bigendian flag throughout code (qemu, ISACaller, tests)
* started running helloworld.bin again
today:
* fixed simple bug in PowerDecoder2, OP_B was not setting LR register write
* added LD/ST cacheing-inhibit instructions
so that's enough to get helloworld "operational" as far as running
without a UART peripheral is concerned. the next stage will be to
drop a UART peripheral (simulated or otherwise) onto the memory bus.
these are what the ld/st cache-inhibit instructions are supposed to be
used for, to access the peripheral at address 0xc0000000.
l.
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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* Re: [libre-riscv-dev] daily kan-ban update 12jul2020
2020-07-12 12:43 [libre-riscv-dev] daily kan-ban update 12jul2020 Luke Kenneth Casson Leighton
@ 2020-07-13 1:48 ` Jacob Lifshay
2020-07-13 3:49 ` Jacob Lifshay
0 siblings, 1 reply; 6+ messages in thread
From: Jacob Lifshay @ 2020-07-13 1:48 UTC (permalink / raw)
To: Libre-RISCV General Development
today:
found the root cause and created a fix for nmigen's zeros in vcd issue
Finished off the pull request for adding string-typed vcd variables
and for outputting values as strings instead of u64 values:
https://github.com/sgpthomas/vcdump/pull/1
Jacob
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* Re: [libre-riscv-dev] daily kan-ban update 12jul2020
2020-07-13 1:48 ` Jacob Lifshay
@ 2020-07-13 3:49 ` Jacob Lifshay
2020-07-13 9:42 ` Luke Kenneth Casson Leighton
0 siblings, 1 reply; 6+ messages in thread
From: Jacob Lifshay @ 2020-07-13 3:49 UTC (permalink / raw)
To: Libre-RISCV General Development
I also just proposed adding a API to nmigen to output VCD events. You
can think of them as the VCD file having certain times marked. I think
they would be useful for unit tests since we could output them to the
VCD file when we read all the variables in a unit test.
https://github.com/nmigen/nmigen/issues/431
Jacob
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* Re: [libre-riscv-dev] daily kan-ban update 12jul2020
2020-07-13 3:49 ` Jacob Lifshay
@ 2020-07-13 9:42 ` Luke Kenneth Casson Leighton
2020-07-13 9:51 ` Jacob Lifshay
0 siblings, 1 reply; 6+ messages in thread
From: Luke Kenneth Casson Leighton @ 2020-07-13 9:42 UTC (permalink / raw)
To: Libre-RISCV General Development
On Mon, Jul 13, 2020 at 4:49 AM Jacob Lifshay <programmerjake@gmail.com> wrote:
>
> I also just proposed adding a API to nmigen to output VCD events. You
> can think of them as the VCD file having certain times marked. I think
> they would be useful for unit tests since we could output them to the
> VCD file when we read all the variables in a unit test.
so... this is like... debug log notifications? (which are missing
from nmigen, and it's quite a nuisance).
l.
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* Re: [libre-riscv-dev] daily kan-ban update 12jul2020
2020-07-13 9:42 ` Luke Kenneth Casson Leighton
@ 2020-07-13 9:51 ` Jacob Lifshay
2020-07-13 9:58 ` Luke Kenneth Casson Leighton
0 siblings, 1 reply; 6+ messages in thread
From: Jacob Lifshay @ 2020-07-13 9:51 UTC (permalink / raw)
To: Libre-RISCV General Development
On Mon, Jul 13, 2020, 02:43 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
wrote:
> On Mon, Jul 13, 2020 at 4:49 AM Jacob Lifshay <programmerjake@gmail.com>
> wrote:
> >
> > I also just proposed adding a API to nmigen to output VCD events. You
> > can think of them as the VCD file having certain times marked. I think
> > they would be useful for unit tests since we could output them to the
> > VCD file when we read all the variables in a unit test.
>
> so... this is like... debug log notifications? (which are missing
> from nmigen, and it's quite a nuisance).
>
kinda -- they show up as signals in gtkwave
>
additional info after 30s of searching:
https://stackoverflow.com/questions/33095017/how-to-specify-annotations-in-vcd-files
Jacob
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* Re: [libre-riscv-dev] daily kan-ban update 12jul2020
2020-07-13 9:51 ` Jacob Lifshay
@ 2020-07-13 9:58 ` Luke Kenneth Casson Leighton
0 siblings, 0 replies; 6+ messages in thread
From: Luke Kenneth Casson Leighton @ 2020-07-13 9:58 UTC (permalink / raw)
To: Libre-RISCV General Development
On Mon, Jul 13, 2020 at 10:51 AM Jacob Lifshay <programmerjake@gmail.com> wrote:
>
> On Mon, Jul 13, 2020, 02:43 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
> wrote:
>
> > On Mon, Jul 13, 2020 at 4:49 AM Jacob Lifshay <programmerjake@gmail.com>
> > wrote:
> > >
> > > I also just proposed adding a API to nmigen to output VCD events. You
> > > can think of them as the VCD file having certain times marked. I think
> > > they would be useful for unit tests since we could output them to the
> > > VCD file when we read all the variables in a unit test.
> >
> > so... this is like... debug log notifications? (which are missing
> > from nmigen, and it's quite a nuisance).
> >
>
> kinda -- they show up as signals in gtkwave
that's good. it's close enough. what would be better (if it's at all
possible): yield ev1("some additional debug info %d" %
some_runtime_variable) although just the event (at all) would be
extremely useful.
> additional info after 30s of searching:
> https://stackoverflow.com/questions/33095017/how-to-specify-annotations-in-vcd-files
except without nmigen support it's moot.
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2020-07-12 12:43 [libre-riscv-dev] daily kan-ban update 12jul2020 Luke Kenneth Casson Leighton
2020-07-13 1:48 ` Jacob Lifshay
2020-07-13 3:49 ` Jacob Lifshay
2020-07-13 9:42 ` Luke Kenneth Casson Leighton
2020-07-13 9:51 ` Jacob Lifshay
2020-07-13 9:58 ` Luke Kenneth Casson Leighton
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