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From: Samuel Falvo II <sam.falvo@gmail.com>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] how do we test external interrupts?
Date: Tue, 28 Jul 2020 07:54:59 -0700
Message-ID: <CAEz=sonuUeOMOHyBw8iezd5t6GjMCRDx=Sr2XauvvcpGV+EnbA@mail.gmail.com> (raw)
In-Reply-To: <CAPweEDySLuS1NVLv71LZ_UXRRdfxWQ5WQ__1wkkx5JY9vS1mWA@mail.gmail.com>

I might be stating the obvious; but, according to
https://www.kernel.org/doc/html/latest/virt/kvm/devices/xive.html, it
looks like XICS is a POWER7- / POWER8-related specification.
Wikipedia indicates POWER7 was released around 2010-ish.  Maybe
finding specs dated about that time would be a good place to look?  (I
tried but wasn't successful.)

On Tue, Jul 28, 2020 at 6:31 AM Luke Kenneth Casson Leighton
<lkcl@lkcl.net> wrote:
>
> i've started on the XICS controller, and have converted both the ICS and
> ICP.  a simple unit test on XICS-ICS shows it to be functional.
>
> however we are hampered in several ways:
>
> 1) there does not appear to exist an actual accessible specification.
>
> 2) the only implementations are source code (linux kernel, qemu)
>
> 3) nobody else has written unit tests
>
> 4) given that XICS is involved in *external* interrupts, how do we even
> *begin* to write a unit test that runs under e.g. qemu and the simulator,
> here??
>
> so i'd like to open up the discussion to develop a strategy here.
>
> my feeling is that we may have to create a simulated peripheral (an
> interrupt driven 16550 UART) in ISACaller which would allow exploration,
> here.
>
> thoughts welcome.
>
> l.
>
>
>
> --
> ---
> crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
> _______________________________________________
> libre-riscv-dev mailing list
> libre-riscv-dev@lists.libre-riscv.org
> http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev



-- 
Samuel A. Falvo II

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Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-28 13:30 Luke Kenneth Casson Leighton
2020-07-28 14:54 ` Samuel Falvo II [this message]
2020-07-28 16:14   ` Luke Kenneth Casson Leighton
2020-07-28 16:41     ` Samuel Falvo II
2020-07-28 16:50       ` Jacob Lifshay
2020-07-28 18:20         ` Luke Kenneth Casson Leighton

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