[libre-riscv-dev] how do we test external interrupts?

From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] how do we test external interrupts?
Date: Tue, 28 Jul 2020 14:30:27 +0100
Message-ID: <CAPweEDySLuS1NVLv71LZ_UXRRdfxWQ5WQ__1wkkx5JY9vS1mWA@mail.gmail.com> (raw)

i've started on the XICS controller, and have converted both the ICS and
ICP.  a simple unit test on XICS-ICS shows it to be functional.

however we are hampered in several ways:

1) there does not appear to exist an actual accessible specification.

2) the only implementations are source code (linux kernel, qemu)

3) nobody else has written unit tests

4) given that XICS is involved in *external* interrupts, how do we even
*begin* to write a unit test that runs under e.g. qemu and the simulator,
here??

so i'd like to open up the discussion to develop a strategy here.

my feeling is that we may have to create a simulated peripheral (an
interrupt driven 16550 UART) in ISACaller which would allow exploration,
here.

thoughts welcome.

l.

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