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From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] daily kan-ban update 13may2020
Date: Wed, 13 May 2020 16:03:21 +0100
Message-ID: <CAPweEDw0vX56mGdvDCJaykQbf3qAS3TLZryprnt5JpL4cggiDA@mail.gmail.com> (raw)
In-Reply-To: <20200513164341.19d30999fa7607f985b2b842@platen-software.de>

On Wed, May 13, 2020 at 3:43 PM Tobias Platen
<libre-soc@platen-software.de> wrote:
>
> On Wed, 13 May 2020 15:33:53 +0100
> Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
>
> > a really useful self-contained sub-task would be to convert this to nmigen:
> > https://github.com/antonblanchard/microwatt/blob/master/countzero.vhdl
> I think I could do this in an hour or less.

ok great.  create a directory in soc.git, src/soc/countzero to work in.
don't commit the VHDL to the repo, reference it in a comment at the top
of countzero.py

also useful as a "very basic" simulation and confirmation of functionality
i'd recommend doing a unit test similar to countzero_tb.vhdl

l.

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Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-13 10:28 Luke Kenneth Casson Leighton
2020-05-13 13:56 ` Tobias Platen
2020-05-13 14:33   ` Luke Kenneth Casson Leighton
2020-05-13 14:43     ` Tobias Platen
2020-05-13 15:03       ` Luke Kenneth Casson Leighton [this message]
2020-05-13 18:07         ` Cole Poirier
2020-05-13 22:02         ` Luke Kenneth Casson Leighton

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