From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] daily kan-ban update 13may2020
Date: Wed, 13 May 2020 11:28:25 +0100
Message-ID: <CAPweEDz8rcJ7ENbJS5tk3pCs7TDSPx11=7cOPFwxRaTBbtW_wg@mail.gmail.com> (raw)
yesterday i started on integrating the LDSTCompUnit into the
scoreboard and immediately ran into a brick wall in the form of the
address-request/release signalling. when go_addr is raised (in
response to req_addr), the LDSTCompUnit is supposed to drop req_addr
one cycle later: instead it stays high.
i also investigated microwatt to find out what the heck is going on
with the register-order-swapping. turns out that different classes of
operations (logical, rotate, arith) have different ordering. why? who
knows.
today i will continue working through the address-negotiation in LDSTCompUnit.
l.
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Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-13 10:28 Luke Kenneth Casson Leighton [this message]
2020-05-13 13:56 ` Tobias Platen
2020-05-13 14:33 ` Luke Kenneth Casson Leighton
2020-05-13 14:43 ` Tobias Platen
2020-05-13 15:03 ` Luke Kenneth Casson Leighton
2020-05-13 18:07 ` Cole Poirier
2020-05-13 22:02 ` Luke Kenneth Casson Leighton
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