[libre-riscv-dev] daily kan-ban update 04aug2020

[libre-riscv-dev] daily kan-ban update 04aug2020

[Luke Kenneth Casson Leighton]

tasks:

*
https://bugs.libre-soc.org/showdependencytree.cgi?id=383&maxdepth=1&hide_resolved=1

yesterday:

* add DMI interface

today:

* in litex sim add an FSM that interacts through the DMI, sets the core in
singlestep mode and gets the PC and other data

i will be able to dump the entire regfile this way and do a diff compare of
libresoc vs microwatt.

this will tell us exactly which instruction being executed is not doing the
correct thing.

l.



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Re: [libre-riscv-dev] daily kan-ban update 04aug2020

[Luke Kenneth Casson Leighton]

On Tue, Aug 4, 2020 at 1:45 PM Luke Kenneth Casson Leighton
<lkcl@lkcl.net> wrote:

> i will be able to dump the entire regfile this way and do a diff compare of libresoc vs microwatt.
>
> this will tell us exactly which instruction being executed is not doing the correct thing.

ta-daaa, which is exactly what occurred.  the wishbone data-bus
request is not getting an "ACK" on a stw instruction, which means i
have a place to start investigating.

hurrah.

l.

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Re: [libre-riscv-dev] daily kan-ban update 04aug2020

[Tobias Platen]

today:

unit test for DualPortSplitter

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Re: [libre-riscv-dev] daily kan-ban update 04aug2020

[Luke Kenneth Casson Leighton]

On Tue, Aug 4, 2020 at 6:19 PM Tobias Platen
<libre-soc@platen-software.de> wrote:
>
> today:
>
> unit test for DualPortSplitter

ok great.  btw you saw that i had to revert a commit that you made:
please do ensure that you commit code that is "working" or at least
doesn't cause other people to not be able to do "work".  i've had to
do this three times now.

as best i can tell when i wrote the unit test for LDSTSplitter, the
"logic" behind LDSTSplitter is correct, however the mask works on
*bits* not bytes (sigh).

also: the left port needs to be for when addr[4] == 0 and the right
port for when addr[4] == 1.  this is achieved with a crossbar on
*both* the LD *and* ST data.

l.

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Re: [libre-riscv-dev] daily kan-ban update 04aug2020

[Tobias Platen]

On Tue, 4 Aug 2020 18:32:34 +0100
Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:

> On Tue, Aug 4, 2020 at 6:19 PM Tobias Platen
> <libre-soc@platen-software.de> wrote:
> >
> > today:
> >
> > unit test for DualPortSplitter
> 
> ok great.  btw you saw that i had to revert a commit that you made:
Yes, I saw 
> please do ensure that you commit code that is "working" or at least
> doesn't cause other people to not be able to do "work".  i've had to
> do this three times now.
> 
> as best i can tell when i wrote the unit test for LDSTSplitter, the
> "logic" behind LDSTSplitter is correct, however the mask works on
> *bits* not bytes (sigh).
> 
> also: the left port needs to be for when addr[4] == 0 and the right
> port for when addr[4] == 1.  this is achieved with a crossbar on
> *both* the LD *and* ST data.
> l.
> 
> _______________________________________________
> libre-riscv-dev mailing list
> libre-riscv-dev@lists.libre-riscv.org
> http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev


-- 
Tobias Platen <libre-soc[at]platen-software[dot]de>

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Re: [libre-riscv-dev] daily kan-ban update 04aug2020

[Tobias Platen]

On Wed, 5 Aug 2020 18:40:58 +0200
Tobias Platen <libre-soc@platen-software.de> wrote:

> On Tue, 4 Aug 2020 18:32:34 +0100
> Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
> 
> > On Tue, Aug 4, 2020 at 6:19 PM Tobias Platen
> > <libre-soc@platen-software.de> wrote:
> > >
> > > today:
> > >
> > > unit test for DualPortSplitter
> > 
> > ok great.  btw you saw that i had to revert a commit that you made:
> Yes, I saw 
> > please do ensure that you commit code that is "working" or at least
> > doesn't cause other people to not be able to do "work".  i've had to
> > do this three times now.
> > 
> > as best i can tell when i wrote the unit test for LDSTSplitter, the
> > "logic" behind LDSTSplitter is correct, however the mask works on
> > *bits* not bytes (sigh).
That might be the reason why I get an error when running the unit tests:
LenExpand 4 1 unsigned(16)
LenExpand 4 1 unsigned(16)
ldm 255 0b11010011
dlm 15 0b1100
dmask 0b11111111000000000000
dmask1 0b1111
dmask 0b1111000000000000
lds
send_ld
waiting
ld data1 0b11010011 0b11000000000000 12 0b1111000000000000
ld data2 16 0b0 0b1101
0b11 0b11010011
Traceback (most recent call last):
  File "addr_split.py", line 270, in <module>
    sim(dut)
  File "addr_split.py", line 261, in sim
    sim.run()
  File "/home/isengaara/Hacking/lSOC/TEST/nmigen/nmigen/sim/pysim.py", line 382, in run
    while self.advance():
  File "/home/isengaara/Hacking/lSOC/TEST/nmigen/nmigen/sim/pysim.py", line 371, in advance
    self._real_step()
  File "/home/isengaara/Hacking/lSOC/TEST/nmigen/nmigen/sim/pysim.py", line 347, in _real_step
    process.run()
  File "/home/isengaara/Hacking/lSOC/TEST/nmigen/nmigen/sim/_pycoro.py", line 120, in run
    self.coroutine.throw(exn)
  File "/home/isengaara/Hacking/lSOC/TEST/nmigen/nmigen/sim/_pycoro.py", line 61, in run
    command = self.coroutine.send(response)
  File "/home/isengaara/Hacking/lSOC/TEST/nmigen/nmigen/sim/pysim.py", line 265, in wrapper
    yield from process()
  File "addr_split.py", line 232, in send_ld
    assert ld_data_o == data
AssertionError
make: *** [Makefile:4: test_ldst_splitter] Fehler 1
I'll investigate that.
> > 
> > also: the left port needs to be for when addr[4] == 0 and the right
> > port for when addr[4] == 1.  this is achieved with a crossbar on
> > *both* the LD *and* ST data.
> > l.
> > 
> > _______________________________________________
> > libre-riscv-dev mailing list
> > libre-riscv-dev@lists.libre-riscv.org
> > http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev
> 
> 
> -- 
> Tobias Platen <libre-soc[at]platen-software[dot]de>
> 
> _______________________________________________
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> libre-riscv-dev@lists.libre-riscv.org
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-- 
Tobias Platen <libre-soc[at]platen-software[dot]de>

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Re: [libre-riscv-dev] daily kan-ban update 04aug2020

[Luke Kenneth Casson Leighton]

On Wed, Aug 5, 2020 at 5:48 PM Tobias Platen
<libre-soc@platen-software.de> wrote:

> > > as best i can tell when i wrote the unit test for LDSTSplitter, the
> > > "logic" behind LDSTSplitter is correct, however the mask works on
> > > *bits* not bytes (sigh).
> That might be the reason why I get an error when running the unit tests:
> LenExpand 4 1 unsigned(16)
> LenExpand 4 1 unsigned(16)

yes.  i started adding an option of expanding to bytes rather than
bits, ran into difficulties and, given that the code is unused
anywhere at the moment, left it.

if you go back through the git logs you will find what i added at the time.

l.

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Re: [libre-riscv-dev] daily kan-ban update 04aug2020

[Tobias Platen]

On Wed, 5 Aug 2020 18:08:04 +0100
Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:

> > > > as best i can tell when i wrote the unit test for LDSTSplitter, the
> > > > "logic" behind LDSTSplitter is correct, however the mask works on
> > > > *bits* not bytes (sigh).
> > That might be the reason why I get an error when running the unit tests:
> > LenExpand 4 1 unsigned(16)
> > LenExpand 4 1 unsigned(16)

I found those two commits in the git history.

commit c4d90bf6e19f4a16adba68b8af9a7ae5005a7062
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Tue Jun 9 18:33:22 2020 +0100

    allow LenExpand to output both byte- and bit- mask expansion

commit f700880e9add726c01ace79e2a36e48faa83946c
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Tue Jun 9 14:01:06 2020 +0100

    expand LenExpand (haha) to cover bytes, with an argument "cover"
    all puns intentional


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Re: [libre-riscv-dev] daily kan-ban update 04aug2020

[Luke Kenneth Casson Leighton]

On Wed, Aug 5, 2020 at 6:37 PM Tobias Platen
<libre-soc@platen-software.de> wrote:
>
> On Wed, 5 Aug 2020 18:08:04 +0100
> Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
>
> > > > > as best i can tell when i wrote the unit test for LDSTSplitter, the
> > > > > "logic" behind LDSTSplitter is correct, however the mask works on
> > > > > *bits* not bytes (sigh).
> > > That might be the reason why I get an error when running the unit tests:
> > > LenExpand 4 1 unsigned(16)
> > > LenExpand 4 1 unsigned(16)
>
> I found those two commits in the git history.

ok so the one you just changed, was this:

diff --git a/src/soc/scoreboard/addr_split.py b/src/soc/scoreboard/addr_split.py
index 0cd546ce..aa99f63c 100644
--- a/src/soc/scoreboard/addr_split.py
+++ b/src/soc/scoreboard/addr_split.py
@@ -100,7 +100,7 @@ class LDSTSplitter(Elaboratable):
         mzero = Const(0, mlen)
         m.submodules.ld1 = ld1 = LDLatch(self.dwidth, self.awidth-dlen, mlen)
         m.submodules.ld2 = ld2 = LDLatch(self.dwidth, self.awidth-dlen, mlen)
-        m.submodules.lenexp = lenexp = LenExpand(self.dlen, cover=8)
+        m.submodules.lenexp = lenexp = LenExpand(self.dlen)

and that got the unit test "working".... by *returning* LDSTSplitter
to do *bit* masking *not* byte masking.

this means that instead of having a 16 bit mask to cover 128 bits of
data,  a whopping *128* bit mask is needed and that's precisely what
we do not want.

l.

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Re: [libre-riscv-dev] daily kan-ban update 04aug2020

[Tobias Platen]

On Wed, 5 Aug 2020 19:39:20 +0100
Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:

> this means that instead of having a 16 bit mask to cover 128 bits of
> data,  a whopping *128* bit mask is needed and that's precisely what
> we do not want.
I think now understand my mistake in thinking and how to solve the problem.

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Re: [libre-riscv-dev] daily kan-ban update 04aug2020

[Luke Kenneth Casson Leighton]

On Wed, Aug 5, 2020 at 7:55 PM Tobias Platen
<libre-soc@platen-software.de> wrote:
>
> On Wed, 5 Aug 2020 19:39:20 +0100
> Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
>
> > this means that instead of having a 16 bit mask to cover 128 bits of
> > data,  a whopping *128* bit mask is needed and that's precisely what
> > we do not want.
> I think now understand my mistake in thinking and how to solve the problem.

cool.

basically, the mask is wishbone "sel", set to a granularity of 8 bits
(one byte) per bit of "sel".

if you read the wishbone spec, concentrating on when "sel" is not just
a single bit, you'll see clearly what is needed.

we are propagating that byte-per-bit mask RIGHT THE WAY THROUGH THE
ENTIRE DESIGN.

it starts at LD/ST - right back when a byte, half-word, word or dword
LD/ST is requested - and goes - will go - through the ENTIRE design

through PortInterface.

through LDSTSplitter.

through DataMerger.

through the L1 cache which will need to respect byte-level masks

through the L2 cache which will need to respect byte-level masks.

through the wishbone buses which will need to respect byte-level masks

through to the DDR / SDR bus which will *ALSO* need to respect byte-level masks.

eeeeverything and i *mean* everyting.

SDR (DDR1, SDRAM) does in fact accept byte-level masks.

if at any time we encounter a memory system which does *NOT* respect
byte-level masks, then we have a problem and will have to rethink.

l.

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