From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] PPC on Talos and Playstation 3
Date: Mon, 30 Mar 2020 18:46:35 +0000
Message-ID: <CAPweEDwbqrhvK-CwCSA7NJemMSAyhjhyXLQQQay=3wQPJaTrAA@mail.gmail.com> (raw)
In-Reply-To: <32516E1C-2A42-4C24-8E67-B8FB051DDD44@gatech.edu>
On Mon, Mar 30, 2020 at 7:35 PM Immanuel, Yehowshua U
<yimmanuel3@gatech.edu> wrote:
> Before I try my hand at an FPU,
yehowshua, you're aware that by choosing to do this, that you'll be
committing over 6 months of your life to the task? that's typically
how long it takes (if not longer).
> Some questions:
> - Do we have any FPU attempt in nMigen, Verilog, or some other language yet that I should be aware of?
> - The POWER ISA 3.0 PDF doc specifies an IEEE 745-1985 compliant mode as well as a faster non-compliant mode - I’m guessing we have to implement both?
sigh. probably.
> - how many stages should I have for the FPU - is there a sweetspot?
we have a trade-off between maximum clock rate and the number of
Function Units (Reservation Stations) needed. so if there are 16-long
pipelines, then that *REQUIRES* 16 Function Units, in order to keep
them fully occupied and still be able to re-associate the result with
the correct FU when it comes back out the pipeline.
if the number of FUs increases too much, we have a problem with the
size of the Dependency Matrices.
i really do not want to go above around 20 FUs. that's still pushing it.
* 6 to 8 of those will be LOAD/STORE.
* at least 2 will be Branch.
* at least 2 will be for predication.
this only leaves 8 (EIGHT!) for ALU operations, which in turn means
that pipelines really cannot go about 8 stages, and that we cannot
have separate FP and INT Function Units.
> - We’re doing a reconfigureable FPU correct? What bit modes does it support?
literally anything. it's defined in a single python dictionary, with
the mantissa and exponent being specified as parameters, by way of a
lookup (the bitwidth) as the key of the python dictionary.
one line of code.
l.
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Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-29 20:17 Immanuel, Yehowshua U
2020-03-29 20:20 ` Immanuel, Yehowshua U
2020-03-29 20:35 ` Jacob Lifshay
2020-03-29 21:01 ` Luke Kenneth Casson Leighton
2020-03-30 6:56 ` Lauri Kasanen
2020-03-30 7:12 ` Jacob Lifshay
2020-03-30 7:32 ` Lauri Kasanen
2020-03-30 7:52 ` Jacob Lifshay
2020-03-30 8:05 ` Lauri Kasanen
2020-03-30 18:07 ` Jacob Lifshay
2020-03-30 18:12 ` Immanuel, Yehowshua U
2020-03-30 18:16 ` Jacob Lifshay
2020-03-30 18:35 ` Immanuel, Yehowshua U
2020-03-30 18:36 ` Immanuel, Yehowshua U
2020-03-30 18:46 ` Luke Kenneth Casson Leighton [this message]
2020-03-30 18:57 ` Immanuel, Yehowshua U
2020-03-30 19:09 ` Luke Kenneth Casson Leighton
2020-03-30 19:20 ` Immanuel, Yehowshua U
2020-03-30 19:25 ` Luke Kenneth Casson Leighton
2020-03-30 19:35 ` Immanuel, Yehowshua U
2020-03-30 19:45 ` Jacob Lifshay
2020-03-30 19:46 ` Immanuel, Yehowshua U
2020-03-30 22:02 ` Luke Kenneth Casson Leighton
2020-03-30 19:01 ` Jacob Lifshay
2020-03-30 19:20 ` Luke Kenneth Casson Leighton
2020-03-31 21:57 ` Michael Nolan
2020-03-31 23:01 ` Luke Kenneth Casson Leighton
2020-04-01 0:23 ` Immanuel, Yehowshua U
2020-04-01 0:44 ` [libre-riscv-dev] additional ddr3 interfaces Jacob Lifshay
2020-04-01 0:47 ` Immanuel, Yehowshua U
2020-04-01 1:01 ` Jacob Lifshay
2020-04-01 11:10 ` Luke Kenneth Casson Leighton
2020-04-01 15:19 ` Staf Verhaegen
2020-04-01 15:42 ` Luke Kenneth Casson Leighton
2020-04-01 11:00 ` [libre-riscv-dev] PPC on Talos and Playstation 3 Luke Kenneth Casson Leighton
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