From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] go die/cancel signals in fsm
Date: Wed, 22 Jul 2020 10:51:17 +0100
Message-ID: <CAPweEDwpQY8oH33GjV=P=zmXP5uCKUMK3HnEoFEA1snfg32Mtw@mail.gmail.com> (raw)
In-Reply-To: <CAC2bXD4+-OuvUk7m1s2F4pZZgkgaYL9RP_thL_ntL0QDdtkhfQ@mail.gmail.com>
On Wed, Jul 22, 2020 at 3:01 AM Jacob Lifshay <programmerjake@gmail.com> wrote:
>
> I looked through the vcd generated for soc.simple.test.test_core and
> was unable to locate the signals used to tell the pipeline stages that
> the instruction they are currently operating on is canceled.
that's because we're using SimpleHandshakeRedir rather than
MaskCancellable, and are not going to do cancellation in the 180nm
core unless we get more people, and i can focus in the remaining very
short amount of time on doing absolutely nothing but add in the
Dependency Matrices.
three months is already far too short to even consider doing that, so
it is extremely unlikely to be added.
> This is
> needed to not have to wait 63(!) more clock cycles for a canceled div
> instruction to finish computing before another div instruction can be
> started.
indeed.
ok so i added some code comments explaining what goes into CommonPipeSpec:
https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=71af4fadd8a431079df13fc5812d745c133074be
i'll also update the README...
https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=593c41881b455aeeb19fe98071647d7b4ffca15c
l.
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Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-22 2:01 Jacob Lifshay
2020-07-22 9:51 ` Luke Kenneth Casson Leighton [this message]
2020-07-22 12:27 ` Luke Kenneth Casson Leighton
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