* [libre-riscv-dev] go die/cancel signals in fsm @ 2020-07-22 2:01 Jacob Lifshay 2020-07-22 9:51 ` Luke Kenneth Casson Leighton 0 siblings, 1 reply; 3+ messages in thread From: Jacob Lifshay @ 2020-07-22 2:01 UTC (permalink / raw) To: Libre-RISCV General Development I looked through the vcd generated for soc.simple.test.test_core and was unable to locate the signals used to tell the pipeline stages that the instruction they are currently operating on is canceled. This is needed to not have to wait 63(!) more clock cycles for a canceled div instruction to finish computing before another div instruction can be started. Help wanted, Jacob _______________________________________________ libre-riscv-dev mailing list libre-riscv-dev@lists.libre-riscv.org http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev ^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [libre-riscv-dev] go die/cancel signals in fsm 2020-07-22 2:01 [libre-riscv-dev] go die/cancel signals in fsm Jacob Lifshay @ 2020-07-22 9:51 ` Luke Kenneth Casson Leighton 2020-07-22 12:27 ` Luke Kenneth Casson Leighton 0 siblings, 1 reply; 3+ messages in thread From: Luke Kenneth Casson Leighton @ 2020-07-22 9:51 UTC (permalink / raw) To: Libre-RISCV General Development On Wed, Jul 22, 2020 at 3:01 AM Jacob Lifshay <programmerjake@gmail.com> wrote: > > I looked through the vcd generated for soc.simple.test.test_core and > was unable to locate the signals used to tell the pipeline stages that > the instruction they are currently operating on is canceled. that's because we're using SimpleHandshakeRedir rather than MaskCancellable, and are not going to do cancellation in the 180nm core unless we get more people, and i can focus in the remaining very short amount of time on doing absolutely nothing but add in the Dependency Matrices. three months is already far too short to even consider doing that, so it is extremely unlikely to be added. > This is > needed to not have to wait 63(!) more clock cycles for a canceled div > instruction to finish computing before another div instruction can be > started. indeed. ok so i added some code comments explaining what goes into CommonPipeSpec: https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=71af4fadd8a431079df13fc5812d745c133074be i'll also update the README... https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=593c41881b455aeeb19fe98071647d7b4ffca15c l. _______________________________________________ libre-riscv-dev mailing list libre-riscv-dev@lists.libre-riscv.org http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev ^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [libre-riscv-dev] go die/cancel signals in fsm 2020-07-22 9:51 ` Luke Kenneth Casson Leighton @ 2020-07-22 12:27 ` Luke Kenneth Casson Leighton 0 siblings, 0 replies; 3+ messages in thread From: Luke Kenneth Casson Leighton @ 2020-07-22 12:27 UTC (permalink / raw) To: Libre-RISCV General Development On Wed, Jul 22, 2020 at 10:51 AM Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote: > > This is > > needed to not have to wait 63(!) more clock cycles for a canceled div > > instruction to finish computing before another div instruction can be > > started. > > indeed. for now, you can see that issuer.py is a FSM: https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/issuer.py;hb=HEAD#l124 so there's not going to be any cancellation. instructions are done one at a time, total freeze until the instruction is completed. l. _______________________________________________ libre-riscv-dev mailing list libre-riscv-dev@lists.libre-riscv.org http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev ^ permalink raw reply [flat|nested] 3+ messages in thread
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