* [libre-riscv-dev] GPU Drivers ROCM
@ 2020-06-06 1:29 Yehowshua
2020-06-06 2:10 ` Luke Kenneth Casson Leighton
0 siblings, 1 reply; 2+ messages in thread
From: Yehowshua @ 2020-06-06 1:29 UTC (permalink / raw)
To: Libre-RISCV General Development
It recently occurred to me that the entire ROCM stack is open.
ROCM also has, OpenGL, Vulkan, OpenCL, and CUDA -> HIP
frontends.
At the very bottom of ROCM sits llvm which emits AMD GPU opcodes.
It **should be possible to modify this emitter for our GPU. Then we’d virtually
have to do little to no work.
I’m actively investigating if this is possible and am trying to start a conversation
with some ROCM engineers.
Yehowshua
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [libre-riscv-dev] GPU Drivers ROCM
2020-06-06 1:29 [libre-riscv-dev] GPU Drivers ROCM Yehowshua
@ 2020-06-06 2:10 ` Luke Kenneth Casson Leighton
0 siblings, 0 replies; 2+ messages in thread
From: Luke Kenneth Casson Leighton @ 2020-06-06 2:10 UTC (permalink / raw)
To: Libre-RISCV General Development
On Saturday, June 6, 2020, Yehowshua <yimmanuel3@gatech.edu> wrote:
> It recently occurred to me that the entire ROCM stack is open.
> ROCM also has, OpenGL, Vulkan, OpenCL, and CUDA -> HIP
> frontends.
https://github.com/RadeonOpenCompute/ROCm
> At the very bottom of ROCM sits llvm which emits AMD GPU opcodes.
according to the diagram, NVIDIA CUDA GPU opcodes as well
>
> It **should be possible to modify this emitter for our GPU. Then we’d
> virtually
> have to do little to no work.
indeed.
another possibility is to actively support AMDGPU opcodes.
this is the aporoach taken by MIAOW (a subset of).
> I’m actively investigating if this is possible and am trying to start a
> conversation
> with some ROCM engineers.
remember to emphasise to them that we are doing a hybrid CPUGPU. that the
usual route of a full IPC / RPC mechanism communicating to a foreign remote
architecture is gone, and any complex IPC/RPC inter-kernel bridge code is
entirely gone, replaced with *direct* executed assembly code.
otherwise they will think that the conversation involves us being a
Vivante, or a MALI, and consequently they will think that you are talking
about 10, 20 or greater man-years of work, whereas what you are actually
talking about is of the order of around 1 maybe 2.
l.
--
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, back to index
Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-06-06 1:29 [libre-riscv-dev] GPU Drivers ROCM Yehowshua
2020-06-06 2:10 ` Luke Kenneth Casson Leighton
Libre RISC-V Mailing list Archives (accessible via public-inbox)
Archives are clonable: git clone --mirror https://inbox.libre-soc.org/libre-riscv-dev
Example config snippet for mirrors
AGPL code for this site: git clone https://public-inbox.org/public-inbox.git