[libre-riscv-dev] daily kan-ban update 31jul2020

[libre-riscv-dev] daily kan-ban update 31jul2020

[Luke Kenneth Casson Leighton]

tasks:

*
https://bugs.libre-soc.org/showdependencytree.cgi?id=383&maxdepth=1&hide_resolved=1

yesterday:

* tracked down XICS unit test bug
* investigated litex libresoc simulation kindly provided by florent
* helped jean-paul with direction on "floorplan" version of layout.
* attended hilarious and informative OpenPOWER Virtual Coffee
*

today:

* added ref to powerpc-notebook article
* updated https://libre-soc.org/3d_gpu/ "progress" section
* looked again with puzzlement at the litex simulation.

rest of day:

not sure.  the litex simulation is "acting up", not outputting serial
console data (for microwatt or libresoc), is stopping early and not quite
matching.

microwatt has branch prediction and a L1 cache so examining the wishbone
reads/writes does not give an accurate picture of what it is actually doing.

i would _like_ to do a cycle accurate comparison of log output and find the
discrepancies however this is really not that easy.

this is going to need some thought.

l.



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Re: [libre-riscv-dev] daily kan-ban update 31jul2020

[Luke Kenneth Casson Leighton]

On Friday, July 31, 2020, Luke Kenneth Casson Leighton <lkcl@lkcl.net>
wrote:

not sure.  the litex simulation is "acting up", not outputting serial
> console data (for microwatt or libresoc), is stopping early and not quite
> matching.
>

ok i have some clues from this.  memory LD / STs were at the wrong
addresses.  this led me to investigate the immediate offsets, which turned
out to be unsigned only.

immediates are calculated in power_decoder which was one the first things
written. it is amazing that it has gone unnoticed for so long.

basically we had nowhere near good enough unit test coverage for LD / ST
otherwise this would have been caught far sooner.

l.



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