[libre-riscv-dev] wishbone does not have byte-enable (but it does have user-tags)

[libre-riscv-dev] wishbone does not have byte-enable (but it does have user-tags)

[Luke Kenneth Casson Leighton]

http://cdn.opencores.org/downloads/wbspec_b4.pdf

one of the things that i have assumed is possible to do in wishbone is
to have a bank of byte-enable lines for the memory read/write
requests.  am i correct in thinking that this is what "sel" (as an
array) is for?

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/minerva/wishbone.py;hb=HEAD#l16

also i've noticed that there is the concept of user and cycle "tags"
which can be optionally added.  this would give us a way to do
cache-line tagging and many other things.

l.

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Re: [libre-riscv-dev] wishbone does not have byte-enable (but it does have user-tags)

[Cole Poirier]

On Jun 9 2020, at 10:10 am, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
 
> also i've noticed that there is the concept of user and cycle "tags"
> which can be optionally added.  this would give us a way to do
> cache-line tagging and many other things.

I have an ignorant question about wishbone. Is it possible that there is
functionality in OpenCAPI that would be beneficial to extend wishbone
with, and not time prohibitive (not for Oct 2020 tapeout but for the
quad-core gpu capable version)? This is assuming that implementing a
part of OpenCAPI in wishbone is legally permitted, which I am also
ignorant of.

Cole



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Re: [libre-riscv-dev] wishbone does not have byte-enable (but it does have user-tags)

[Luke Kenneth Casson Leighton]

On Tue, Jun 9, 2020 at 8:18 PM Cole Poirier <colepoirier@gmail.com> wrote:
>
> On Jun 9 2020, at 10:10 am, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
>
> > also i've noticed that there is the concept of user and cycle "tags"
> > which can be optionally added.  this would give us a way to do
> > cache-line tagging and many other things.
>
> I have an ignorant question about wishbone. Is it possible that there is
> functionality in OpenCAPI that would be beneficial to extend wishbone
> with,

honestly absolutely no idea.  someone else might know.

l.

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Re: [libre-riscv-dev] wishbone does not have byte-enable (but it does have user-tags)

[Cole Poirier]

On Jun 9 2020, at 1:17 pm, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
> On Tue, Jun 9, 2020 at 8:18 PM Cole Poirier <colepoirier@gmail.com> wrote:
>> I have an ignorant question about wishbone. Is it possible that there is
>> functionality in OpenCAPI that would be beneficial to extend wishbone
>> with,
> 
> honestly absolutely no idea.  someone else might know.

Worth me raising a new bug report about this? Potentially for a deferred
discussion on comp.arch or with some POWER devs?

Cole

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Re: [libre-riscv-dev] wishbone does not have byte-enable (but it does have user-tags)

[Luke Kenneth Casson Leighton]

On Wed, Jun 10, 2020 at 10:33 PM Cole Poirier <colepoirier@gmail.com> wrote:
>
> On Jun 9 2020, at 1:17 pm, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
> > On Tue, Jun 9, 2020 at 8:18 PM Cole Poirier <colepoirier@gmail.com> wrote:
> >> I have an ignorant question about wishbone. Is it possible that there is
> >> functionality in OpenCAPI that would be beneficial to extend wishbone
> >> with,
> >
> > honestly absolutely no idea.  someone else might know.
>
> Worth me raising a new bug report about this? Potentially for a deferred
> discussion on comp.arch or with some POWER devs?

yes good idea.

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