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From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Cc: "openpower-hdl-cores@mailinglist.openpowerfoundation.org"
	<openpower-hdl-cores@mailinglist.openpowerfoundation.org>
Subject: Re: [libre-riscv-dev] Power ISA v3.1 bug - parityw
Date: Wed, 27 May 2020 23:09:31 +0100
Message-ID: <CAPweEDyMhDF5x+SWB7_jnEnZXH92MA3cbU1Y9jzmiELpkDFKrA@mail.gmail.com> (raw)
In-Reply-To: <20200527214919.GA307798@thinks.paulus.ozlabs.org>

On Wednesday, May 27, 2020, Paul Mackerras <paulus@ozlabs.org> wrote:

>
> > The description of "least significant bit in each byte" leads me to
> believe
> > that RS[i%8 + 7] should really be RS[i*8+7]. This is also how it is
> > implemented in microwatt
>
> The IBM Power architects have confirmed that it should be
> multiplication rather than remainder, i.e. RS[i*8+7] as you suggest.


super.  i can see from the revisions (3.0B -> 3.1B) that it was copied from
a divmod algorithm.

thanks paul.

l.



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Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-15 15:07 Michael Nolan
2020-05-15 15:09 ` Luke Kenneth Casson Leighton
2020-05-26  5:44 ` [libre-riscv-dev] [OpenPOWER-HDL-Cores] " Paul Mackerras
2020-05-27 21:49 ` Paul Mackerras
2020-05-27 22:09   ` Luke Kenneth Casson Leighton [this message]

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