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From: Paul Mackerras <paulus@ozlabs.org>
To: Michael Nolan <mtnolan2640@gmail.com>
Cc: openpower-hdl-cores@mailinglist.openpowerfoundation.org,
	Libre-RISCV General Development
	<libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] Power ISA v3.1 bug - parityw
Date: Thu, 28 May 2020 07:49:19 +1000
Message-ID: <20200527214919.GA307798@thinks.paulus.ozlabs.org> (raw)
In-Reply-To: <48876f64-f3fa-c616-6710-ba773c89173c@gmail.com>

On Fri, May 15, 2020 at 11:07:12AM -0400, Michael Nolan wrote:
> Hello! I'm with the Libre-SOC team, and was working on testing our
> implementation of the parityw and parityd instructions when I came across
> the following bug in the specification. The specification describes prtyd as
> follows:
> 
> s <- 0
> 
> do i = 0 to 7
> 
>     s <- s (XOR) RS[i%8 + 7]
> 
> RA <- 63'b0 || s
> 
> The least significant bit in each byte of the contents of register RS is
> examined. If there is an odd number of one bits the value 1 is placed into
> register RA; otherwise the value 0 is placed into register RA.
> 
> 
> 
> The description of "least significant bit in each byte" leads me to believe
> that RS[i%8 + 7] should really be RS[i*8+7]. This is also how it is
> implemented in microwatt

The IBM Power architects have confirmed that it should be
multiplication rather than remainder, i.e. RS[i*8+7] as you suggest.

Paul.

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Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-15 15:07 [libre-riscv-dev] " Michael Nolan
2020-05-15 15:09 ` Luke Kenneth Casson Leighton
2020-05-26  5:44 ` [libre-riscv-dev] [OpenPOWER-HDL-Cores] " Paul Mackerras
2020-05-27 21:49 ` Paul Mackerras [this message]
2020-05-27 22:09   ` [libre-riscv-dev] " Luke Kenneth Casson Leighton

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