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From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Cc: openpower-hdl-cores@mailinglist.openpowerfoundation.org
Subject: Re: [libre-riscv-dev] Power ISA v3.1 bug - parityw
Date: Fri, 15 May 2020 16:09:49 +0100
Message-ID: <CAPweEDwgKV_iW6oQ5D3mTkTeBqaKZ2j8ZU8-VG0hKb7A35EvEg@mail.gmail.com> (raw)
In-Reply-To: <48876f64-f3fa-c616-6710-ba773c89173c@gmail.com>

On Fri, May 15, 2020 at 4:07 PM Michael Nolan <mtnolan2640@gmail.com> wrote:

> s <- 0
>
> do i = 0 to 7
>
>      s <- s (XOR) RS[i%8 + 7]

we note that in V3.0B this was s <- s / RS[I%8 + 7] - divide and
modulo rather than XOR and multiply.

l.

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Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-15 15:07 Michael Nolan
2020-05-15 15:09 ` Luke Kenneth Casson Leighton [this message]
2020-05-26  5:44 ` [libre-riscv-dev] [OpenPOWER-HDL-Cores] " Paul Mackerras
2020-05-27 21:49 ` Paul Mackerras
2020-05-27 22:09   ` [libre-riscv-dev] " Luke Kenneth Casson Leighton

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