[libre-riscv-dev] Power ISA v3.1 bug

* [libre-riscv-dev] Power ISA v3.1 bug - parityw
@ 2020-05-15 15:07 Michael Nolan
  2020-05-15 15:09 ` Luke Kenneth Casson Leighton
                   ` (2 more replies)
  0 siblings, 3 replies; 5+ messages in thread
From: Michael Nolan @ 2020-05-15 15:07 UTC (permalink / raw)
  To: openpower-hdl-cores, Libre-RISCV General Development

Hello! I'm with the Libre-SOC team, and was working on testing our 
implementation of the parityw and parityd instructions when I came 
across the following bug in the specification. The specification 
describes prtyd as follows:

s <- 0

do i = 0 to 7

     s <- s (XOR) RS[i%8 + 7]

RA <- 63'b0 || s

The least significant bit in each byte of the contents of register RS is 
examined. If there is an odd number of one bits the value 1 is placed 
into register RA; otherwise the value 0 is placed into register RA.

The description of "least significant bit in each byte" leads me to 
believe that RS[i%8 + 7] should really be RS[i*8+7]. This is also how it 
is implemented in microwatt

https://github.com/antonblanchard/microwatt/blob/master/ppc_fx_insns.vhdl 
line 297:

     function ppc_prtyd (rs: std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
         variable tmp : std_ulogic;
         variable ret : std_ulogic_vector(63 downto 0);
     begin
         ret := (others => '0');

         tmp := '0';
         for i in 0 to 7 loop
             tmp := tmp xor rs(i*8);
         end loop;

         ret(0) := tmp;
         return ret;
     end;

Could you confirm whether RS[i*8+7] is the correct behavior?

Thanks,
Michael Nolan

P.S. Our discussion on the Libre-SOC bugzilla: https://bugs.libre-soc.org/show_bug.cgi?id=305#c73

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