* [libre-riscv-dev] Power ISA v3.1 bug - parityw
@ 2020-05-15 15:07 Michael Nolan
2020-05-15 15:09 ` Luke Kenneth Casson Leighton
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Michael Nolan @ 2020-05-15 15:07 UTC (permalink / raw)
To: openpower-hdl-cores, Libre-RISCV General Development
Hello! I'm with the Libre-SOC team, and was working on testing our
implementation of the parityw and parityd instructions when I came
across the following bug in the specification. The specification
describes prtyd as follows:
s <- 0
do i = 0 to 7
s <- s (XOR) RS[i%8 + 7]
RA <- 63'b0 || s
The least significant bit in each byte of the contents of register RS is
examined. If there is an odd number of one bits the value 1 is placed
into register RA; otherwise the value 0 is placed into register RA.
The description of "least significant bit in each byte" leads me to
believe that RS[i%8 + 7] should really be RS[i*8+7]. This is also how it
is implemented in microwatt
https://github.com/antonblanchard/microwatt/blob/master/ppc_fx_insns.vhdl
line 297:
function ppc_prtyd (rs: std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
variable tmp : std_ulogic;
variable ret : std_ulogic_vector(63 downto 0);
begin
ret := (others => '0');
tmp := '0';
for i in 0 to 7 loop
tmp := tmp xor rs(i*8);
end loop;
ret(0) := tmp;
return ret;
end;
Could you confirm whether RS[i*8+7] is the correct behavior?
Thanks,
Michael Nolan
P.S. Our discussion on the Libre-SOC bugzilla: https://bugs.libre-soc.org/show_bug.cgi?id=305#c73
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [libre-riscv-dev] Power ISA v3.1 bug - parityw
2020-05-15 15:07 [libre-riscv-dev] Power ISA v3.1 bug - parityw Michael Nolan
@ 2020-05-15 15:09 ` Luke Kenneth Casson Leighton
2020-05-26 5:44 ` [libre-riscv-dev] [OpenPOWER-HDL-Cores] " Paul Mackerras
2020-05-27 21:49 ` Paul Mackerras
2 siblings, 0 replies; 5+ messages in thread
From: Luke Kenneth Casson Leighton @ 2020-05-15 15:09 UTC (permalink / raw)
To: Libre-RISCV General Development; +Cc: openpower-hdl-cores
On Fri, May 15, 2020 at 4:07 PM Michael Nolan <mtnolan2640@gmail.com> wrote:
> s <- 0
>
> do i = 0 to 7
>
> s <- s (XOR) RS[i%8 + 7]
we note that in V3.0B this was s <- s / RS[I%8 + 7] - divide and
modulo rather than XOR and multiply.
l.
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] Power ISA v3.1 bug - parityw
2020-05-15 15:07 [libre-riscv-dev] Power ISA v3.1 bug - parityw Michael Nolan
2020-05-15 15:09 ` Luke Kenneth Casson Leighton
@ 2020-05-26 5:44 ` " Paul Mackerras
2020-05-27 21:49 ` Paul Mackerras
2 siblings, 0 replies; 5+ messages in thread
From: Paul Mackerras @ 2020-05-26 5:44 UTC (permalink / raw)
To: Michael Nolan; +Cc: openpower-hdl-cores, Libre-RISCV General Development
On Fri, May 15, 2020 at 11:07:12AM -0400, Michael Nolan wrote:
> Hello! I'm with the Libre-SOC team, and was working on testing our
> implementation of the parityw and parityd instructions when I came across
> the following bug in the specification. The specification describes prtyd as
> follows:
>
> s <- 0
>
> do i = 0 to 7
>
> s <- s (XOR) RS[i%8 + 7]
>
> RA <- 63'b0 || s
>
> The least significant bit in each byte of the contents of register RS is
> examined. If there is an odd number of one bits the value 1 is placed into
> register RA; otherwise the value 0 is placed into register RA.
>
>
>
> The description of "least significant bit in each byte" leads me to believe
> that RS[i%8 + 7] should really be RS[i*8+7]. This is also how it is
> implemented in microwatt
Right, and microwatt matches POWER9, so POWER9 implements "*" as well.
I have asked the IBM architects for confirmation, and I'll let you
know what they say. For now I think it's pretty safe to go ahead with
"*", since "*" is clearly what existing software expects.
Paul.
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] Power ISA v3.1 bug - parityw
2020-05-15 15:07 [libre-riscv-dev] Power ISA v3.1 bug - parityw Michael Nolan
2020-05-15 15:09 ` Luke Kenneth Casson Leighton
2020-05-26 5:44 ` [libre-riscv-dev] [OpenPOWER-HDL-Cores] " Paul Mackerras
@ 2020-05-27 21:49 ` Paul Mackerras
2020-05-27 22:09 ` [libre-riscv-dev] " Luke Kenneth Casson Leighton
2 siblings, 1 reply; 5+ messages in thread
From: Paul Mackerras @ 2020-05-27 21:49 UTC (permalink / raw)
To: Michael Nolan; +Cc: openpower-hdl-cores, Libre-RISCV General Development
On Fri, May 15, 2020 at 11:07:12AM -0400, Michael Nolan wrote:
> Hello! I'm with the Libre-SOC team, and was working on testing our
> implementation of the parityw and parityd instructions when I came across
> the following bug in the specification. The specification describes prtyd as
> follows:
>
> s <- 0
>
> do i = 0 to 7
>
> s <- s (XOR) RS[i%8 + 7]
>
> RA <- 63'b0 || s
>
> The least significant bit in each byte of the contents of register RS is
> examined. If there is an odd number of one bits the value 1 is placed into
> register RA; otherwise the value 0 is placed into register RA.
>
>
>
> The description of "least significant bit in each byte" leads me to believe
> that RS[i%8 + 7] should really be RS[i*8+7]. This is also how it is
> implemented in microwatt
The IBM Power architects have confirmed that it should be
multiplication rather than remainder, i.e. RS[i*8+7] as you suggest.
Paul.
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [libre-riscv-dev] Power ISA v3.1 bug - parityw
2020-05-27 21:49 ` Paul Mackerras
@ 2020-05-27 22:09 ` " Luke Kenneth Casson Leighton
0 siblings, 0 replies; 5+ messages in thread
From: Luke Kenneth Casson Leighton @ 2020-05-27 22:09 UTC (permalink / raw)
To: Libre-RISCV General Development; +Cc: openpower-hdl-cores
On Wednesday, May 27, 2020, Paul Mackerras <paulus@ozlabs.org> wrote:
>
> > The description of "least significant bit in each byte" leads me to
> believe
> > that RS[i%8 + 7] should really be RS[i*8+7]. This is also how it is
> > implemented in microwatt
>
> The IBM Power architects have confirmed that it should be
> multiplication rather than remainder, i.e. RS[i*8+7] as you suggest.
super. i can see from the revisions (3.0B -> 3.1B) that it was copied from
a divmod algorithm.
thanks paul.
l.
--
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, back to index
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-05-15 15:07 [libre-riscv-dev] Power ISA v3.1 bug - parityw Michael Nolan
2020-05-15 15:09 ` Luke Kenneth Casson Leighton
2020-05-26 5:44 ` [libre-riscv-dev] [OpenPOWER-HDL-Cores] " Paul Mackerras
2020-05-27 21:49 ` Paul Mackerras
2020-05-27 22:09 ` [libre-riscv-dev] " Luke Kenneth Casson Leighton
Libre RISC-V Mailing list Archives (accessible via public-inbox)
Archives are clonable: git clone --mirror https://inbox.libre-soc.org/libre-riscv-dev
Example config snippet for mirrors
AGPL code for this site: git clone https://public-inbox.org/public-inbox.git