[libre-riscv-dev] Rough timing estimate in yosys

[libre-riscv-dev] Rough timing estimate in yosys

[Michael Nolan]

With all the work going on designing functional units, I was wondering 
if there was a way to get a rough estimate of the maximum frequency a 
module can run at. I can get the longest path from running yosys -p 
"read_ilang module.il; synth; ltp", but that just prints out the cells 
between register A and register B. I realize that the actual timing is 
going to depend on layout, but is there a way to get a rough estimate, 
say by passing in a cell library or just a rule of thumb of ~500ps per cell?


On a semi-related note, running ltp on a pipeline shows that there's a 
bunch of loops.

 From running synth and ltp on the logical pipeline:

Warning: Detected loop at \stage_o$next [63] in pipe
Warning: Detected loop at \stage_o$next [62] in pipe
Warning: Detected loop at \stage_o$next [61] in pipe
Warning: Detected loop at \stage_o$next [60] in pipe
Warning: Detected loop at \stage_o$next [59] in pipe
Warning: Detected loop at \stage_o$next [58] in pipe
Warning: Detected loop at \stage_o$next [57] in pipe
Warning: Detected loop at \stage_o$next [56] in pipe
Warning: Detected loop at \stage_o$next [55] in pipe
Warning: Detected loop at \stage_o$next [54] in pipe
Warning: Detected loop at \stage_o$next [53] in pipe
Warning: Detected loop at \stage_o$next [52] in pipe
Warning: Detected loop at \stage_o$next [51] in pipe
Warning: Detected loop at \stage_o$next [50] in pipe
Warning: Detected loop at \stage_o$next [49] in pipe
Warning: Detected loop at \stage_o$next [48] in pipe
Warning: Detected loop at \stage_o$next [47] in pipe
Warning: Detected loop at \stage_o$next [46] in pipe

Is this supposed to happen?

--Michael


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Re: [libre-riscv-dev] Rough timing estimate in yosys

[Luke Kenneth Casson Leighton]

On Monday, May 18, 2020, Michael Nolan <mtnolan2640@gmail.com> wrote:

> With all the work going on designing functional units, I was wondering if
> there was a way to get a rough estimate of the maximum frequency a module
> can run at. I can get the longest path from running yosys -p "read_ilang
> module.il; synth; ltp", but that just prints out the cells between
> register A and register B.


oh, good.  that's a useful discovery.



> I realize that the actual timing is going to depend on layout, but is
> there a way to get a rough estimate, say by passing in a cell library or
> just a rule of thumb of ~500ps per cell?


i believe it is calculated based on the switching time of a given
transistor, at both the geometry, and also a given voltage.

a chain of such transistors is then multiplied by the longest path.

at the speeds we are doing, speed of light is not a major factor: it will
be however at 28nm or below.

also affecting the switching time is the fanout.  if one gate tries to
drive 200 clearly this will either fail or just take a hell of a long time.

to solve that, buffers must be inserted into the line and of course those
also add switching delay.




>
> On a semi-related note, running ltp on a pipeline shows that there's a
> bunch of loops.
>
> From running synth and ltp on the logical pipeline:
>
> Warning: Detected loop at \stage_o$next [63] in pipe


hmm i do not know.

we are doing an design where the registers can be held until acknowledged
by ready/valid signalling: it's possible that the storage of the register
is interpreted as "a loop".

can you raise a bugreport about it so thatbit can be investigated?  mention
that a small unit test should be made.

l.



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Re: [libre-riscv-dev] Rough timing estimate in yosys

[Luke Kenneth Casson Leighton]

On Monday, May 18, 2020, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:

>
>> Warning: Detected loop at \stage_o$next [63] in pipe
>
>
> we are doing an design where the registers can be held until acknowledged
> by ready/valid signalling: it's possible that the storage of the register
> is interpreted as "a loop".
>
> can you raise a bugreport about it so thatbit can be investigated?
> mention that a small unit test should be made.
>

 https://bugs.libre-soc.org/attachment.cgi?id=55&action=edit

ok yes that's fine.



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