* [libre-riscv-dev] daily kan-ban update 16jul2020
@ 2020-07-17 4:32 Jacob Lifshay
2020-07-17 6:38 ` Luke Kenneth Casson Leighton
2020-07-17 17:13 ` Luke Kenneth Casson Leighton
0 siblings, 2 replies; 3+ messages in thread
From: Jacob Lifshay @ 2020-07-17 4:32 UTC (permalink / raw)
To: Libre-RISCV General Development
today:
attended virtual coffee meeting -- lots of interesting conversation, like usual
added code to switch out div pipeline's udivrem core to different
implementations -- added an implementation that uses nmigen's div and
rem operators for testing rest of div pipeline -- will add a FSM-based
implementation soon
Jacob
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* Re: [libre-riscv-dev] daily kan-ban update 16jul2020
2020-07-17 4:32 [libre-riscv-dev] daily kan-ban update 16jul2020 Jacob Lifshay
@ 2020-07-17 6:38 ` Luke Kenneth Casson Leighton
2020-07-17 17:13 ` Luke Kenneth Casson Leighton
1 sibling, 0 replies; 3+ messages in thread
From: Luke Kenneth Casson Leighton @ 2020-07-17 6:38 UTC (permalink / raw)
To: Libre-RISCV General Development
On Friday, July 17, 2020, Jacob Lifshay <programmerjake@gmail.com> wrote:
> today:
> attended virtual coffee meeting -- lots of interesting conversation, like
> usual
yeah :)
>
> added code to switch out div pipeline's udivrem core to different
> implementations --
i'm tempted to suggest making it possible to select the different
implementations, you know, by the soc.config structures you can see
building up, there.
then the code is still around and useable when we do the larger cores and
sqrt and rsqrt make it worthwhile to use pipelines.
but the abstraction layers building up because of that approach is getting
really high.
> added an implementation that uses nmigen's div and
> rem operators for testing rest of div pipeline -- will add a FSM-based
> implementation soon
star.
--
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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* Re: [libre-riscv-dev] daily kan-ban update 16jul2020
2020-07-17 4:32 [libre-riscv-dev] daily kan-ban update 16jul2020 Jacob Lifshay
2020-07-17 6:38 ` Luke Kenneth Casson Leighton
@ 2020-07-17 17:13 ` Luke Kenneth Casson Leighton
1 sibling, 0 replies; 3+ messages in thread
From: Luke Kenneth Casson Leighton @ 2020-07-17 17:13 UTC (permalink / raw)
To: Libre-RISCV General Development
On Fri, Jul 17, 2020 at 5:32 AM Jacob Lifshay <programmerjake@gmail.com> wrote:
> added code to switch out div pipeline's udivrem core to different
> implementations -- added an implementation that uses nmigen's div and
> rem operators for testing rest of div pipeline -- will add a FSM-based
> implementation soon
btw jacob i've been re-reading alu_hier.py - both of those classes -
ALU and DummyALU - *are* FSM-based (and obey the pipeline API).
i've taken a tag/snapshot of the pipeline work (div_pipeline) prior to
replacement, so we can always refer back to it. i'm strongly leaning
towards ripping out the entire lot. because of the abstraction of
using the ieee754fp code it's really hard to follow. even with 6 to 8
editor windows open i'm having a hard time keeping up with it.
so feel free to rip out the whole lot ok?
l.
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2020-07-17 4:32 [libre-riscv-dev] daily kan-ban update 16jul2020 Jacob Lifshay
2020-07-17 6:38 ` Luke Kenneth Casson Leighton
2020-07-17 17:13 ` Luke Kenneth Casson Leighton
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