[libre-riscv-dev] daily kan-ban 07may2020 update

[libre-riscv-dev] daily kan-ban 07may2020 update

[Luke Kenneth Casson Leighton]

continuing the daily updates, so everyone knows what everyone is doing.

i worked through the new LD/ST CompUnit, got a first draft which has no
python syntax errors and generates an HDL file, today will be to get its
unit test functional (using the new PortInterface).  if that works quickly
i will move on to integrating it into the score6600 code.

MarketNext are going ahead quickly with a magazine article, i will talk to
them about that today.

we had the bi-weekly call with OpenPOWER Foundation member, Tim Pearson
(Raptor CS), and he pointed us at the LPC Master code (just released) - if
we include this interface in the 180nm ASIC they may end up using it as a
"Boot Management processor" to manage larger POWER9 systems.

l.
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Re: [libre-riscv-dev] daily kan-ban 07may2020 update

[Michael Nolan]

I'm continuing working on the power_pseudo simulator, I think I have the 
condition registers working now. I think carry and overflow handling is 
next.

--Michael


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Re: [libre-riscv-dev] daily kan-ban 07may2020 update

[Tobias Platen]

On Thu, 7 May 2020 14:25:14 -0400
Michael Nolan <mtnolan2640@gmail.com> wrote:

Today I will have a short look at the changes from the last few days. 

Tobias

> I'm continuing working on the power_pseudo simulator, I think I have the 
> condition registers working now. I think carry and overflow handling is 
> next.
> 
> --Michael
> 
> 
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-- 
Tobias Platen <libre-soc[at]platen-software[dot]de>

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Re: [libre-riscv-dev] daily kan-ban 07may2020 update

[Luke Kenneth Casson Leighton]

On Thursday, May 7, 2020, Michael Nolan <mtnolan2640@gmail.com> wrote:

> I'm continuing working on the power_pseudo simulator, I think I have the
> condition registers working now. I think carry and overflow handling is
> next.


great.

i could really do with understanding the relationship between condition
registers and branches.

that will allow me to start the Branch Computation Unit.

except probably first i'd need to do the Condition Regfile.

l
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Re: [libre-riscv-dev] daily kan-ban 07may2020 update

[Jacob Lifshay]

I attended the OpenPower virtual coffee meeting, there was an interesting
suggestion to see if we could move to a later tapeout than october, to
avoid burnout due to deadline crunch.

I also weighed in on nmigen signed/unsigned sign extension/zero
extension/truncation operators:
https://github.com/nmigen/nmigen/issues/381

still slowly getting through the load/store unit stuff, progress may be a
little slow since I have a bunch of stuff I need to do at home as well.

Jacob
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Re: [libre-riscv-dev] daily kan-ban 07may2020 update

[Yehowshua]

>  there was an interesting
> suggestion to see if we could move to a later tapeout than october, to
> avoid burnout due to deadline crunch.

Luke and I we’re just discussing this.

Yehowshua
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Re: [libre-riscv-dev] daily kan-ban 07may2020 update

[Luke Kenneth Casson Leighton]

On Friday, May 8, 2020, Jacob Lifshay <programmerjake@gmail.com> wrote:

> I attended the OpenPower virtual coffee meeting, there was an interesting
> suggestion to see if we could move to a later tapeout than october, to
> avoid burnout due to deadline crunch.


i've written to Staf to see what is available.  if you recall we have an
agreement to let him use the Oct2020 slot.  so he is "2nd in queue".

there were other ideas to do a simpler processor for that slot.  however
these would likely go to the *back* of the queue (as a new request for that
slot: "3rd in queue").



>
> I also weighed in on nmigen signed/unsigned sign extension/zero
> extension/truncation operators:
> https://github.com/nmigen/nmigen/issues/381


ah as long as they are explicit rules that in no way change current
behavior (like the signed shift one which caused unit tests to inexplicably
fail for no reason right when we do not need the hassle) we're good.



> still slowly getting through the load/store unit stuff, progress may be a
> little slow since I have a bunch of stuff I need to do at home as well.


ok.

remember, address is divided as:

* bits 0 to 3 plus len turned into 16 bit mask
* bit 4 is for odd-even L1 cache bank selection.
* bits 5 thru 11 go through a 2D AddrMatch, as part of the DMs
* bits 12 and above need checking in 1D, *only* in the L0CacheBuffer.

however if you completely ignore *everything* and i mean everything other
than PortInterface (and the prototype L0CacheBuffer) and just do a
comparison on the full bits 5 thru 48 we can add the information from
AddrMatch later.

the task needed really is genuinely much simpler than it seems. estimated
about... 100 lines of code.

l .


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Re: [libre-riscv-dev] daily kan-ban 07may2020 update

[Staf Verhaegen]

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Luke Kenneth Casson Leighton schreef op vr 08-05-2020 om 03:26 [+0100]:
> On Friday, May 8, 2020, Jacob Lifshay <programmerjake@gmail.com> wrote:
> > I attended the OpenPower virtual coffee meeting, there was an interestingsuggestion to see if we could move to a later tapeout than october, toavoid burnout due to deadline crunch.
> 
> 
> i've written to Staf to see what is available.  if you recall we have anagreement to let him use the Oct2020 slot.  so he is "2nd in queue".
> there were other ideas to do a simpler processor for that slot.  howeverthese would likely go to the *back* of the queue (as a new request for thatslot: "3rd in queue").

As a backup plan I had in mind to tape-out some other CPU like a SwerV RISC-V core from Western Digital. Alternatively some of the budget could be used so I can look into multi-port RAMs and register files; maybe I can have a closer look at a PLL also. These could first be tested on 0.35um which costs a lot less (ca. $5000 vs. ca $20000).

There is question about funding. It takes about 3 months after tape-out to get the chips and then the debugging of the chip can only begin which typically also takes a lot of time. So if we delay the tape-out the completion of the testing of the chip will miss the deadline for the current NLNet funding. I am currently supposed to do the testing of the chip but I won't start that if I don't know if I can get the funding for it.

0.18um TSMC MPW runs are done at least once a month. You can find the schedule online: https://europractice-ic.com/wp-content/uploads/2020/05/General-MPW-EUROPRACTICE-200505-v8.pdf
So last two tape-out dates this year are 18/11 and 2/12 (I think 2/12 was not there in a previous version of the file).
greets,
Staf.



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Re: [libre-riscv-dev] daily kan-ban 07may2020 update

[Yehowshua]

> On May 8, 2020, at 4:41 AM, Staf Verhaegen <staf@fibraservi.eu> wrote:
> 
> 0.18um TSMC MPW runs are done at least once a month. You can find the schedule online: https://europractice-ic.com/wp-content/uploads/2020/05/General-MPW-EUROPRACTICE-200505-v8.pdf <https://europractice-ic.com/wp-content/uploads/2020/05/General-MPW-EUROPRACTICE-200505-v8.pdf>
> So last two tape-out dates this year are 18/11 and 2/12 (I think 2/12 was not there in a previous version of the file).
> greets,
> Staf.


Hello Staf,

What about 2021? Are there slots for say March 2021?
And worst case scenario, I can acquire the needed funds for testing the chip from alternative funding sources no problem.

Yehowshua
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Re: [libre-riscv-dev] daily kan-ban 07may2020 update

[Luke Kenneth Casson Leighton]

On Fri, May 8, 2020 at 9:41 AM Staf Verhaegen <staf@fibraservi.eu> wrote:

> As a backup plan I had in mind to tape-out some other CPU like a SwerV RISC-V core from Western Digital.

which would test the Cell Library (and the Libre development workflow)
very well.  except because it would come from the NLNet budget, it
would remove the opportunity for us to have an NLNet-funded tape-out.


> Alternatively some of the budget could be used so I can look into multi-port RAMs and register files; maybe I can have a closer look at a PLL also.

a Professor at LIP6.fr is happy to design one.


> These could first be tested on 0.35um which costs a lot less (ca. $5000 vs. ca $20000).

if we drop the slot, we should talk that through with NLNet.  they're
critical components so would be good to have.  also that clock-gating
cell.

> There is question about funding. It takes about 3 months after tape-out to get the chips and then the debugging of the chip can only begin which typically also takes a lot of time. So if we delay the tape-out the completion of the testing of the chip will miss the deadline for the current NLNet funding. I am currently supposed to do the testing of the chip but I won't start that if I don't know if I can get the funding for it.

ok so what you're saying is: if we try to do a later date, then we're
outside of the window for not just NLNet funding proposals, but
funding from NLNet *at all*, due to the EU Horizon 2020 conditions
that NLNet-funded projects be 100% completed Q3/4 of 2021.

> 0.18um TSMC MPW runs are done at least once a month. You can find the schedule online: https://europractice-ic.com/wp-content/uploads/2020/05/General-MPW-EUROPRACTICE-200505-v8.pdf

so everyone is aware: these general 180nm MPW runs are not EUR 600 /
sq.mm (the subsidised cost via Staf).  they're 2-3x that level: around
EUR 1100 to 1500


Yehowshua wrote:

> And worst case scenario, I can acquire the needed funds for testing the chip from alternative funding sources no problem.

this is good - it would however not be at the EUR 600 / sq.mm level,
it would be at double that, and also likely need Staf's paid-for
assistance (if you're up for that, Staf?) to act as a firebreak for
the NDAs.

l.

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Re: [libre-riscv-dev] daily kan-ban 07may2020 update

[Luke Kenneth Casson Leighton]

staf tells me he has to focus on a tapeout deadline for a few days.

l.



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Re: [libre-riscv-dev] daily kan-ban 07may2020 update

[Staf Verhaegen]

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Luke Kenneth Casson Leighton schreef op vr 08-05-2020 om 10:08 [+0100]:
> > 0.18um TSMC MPW runs are done at least once a month. You can find the schedule online: https://europractice-ic.com/wp-content/uploads/2020/05/General-MPW-EUROPRACTICE-200505-v8.pdf
> 
> so everyone is aware: these general 180nm MPW runs are not EUR 600 /sq.mm (the subsidised cost via Staf).  they're 2-3x that level: aroundEUR 1100 to 1500
> 
> Yehowshua wrote:
> > And worst case scenario, I can acquire the needed funds for testing the chip from alternative funding sources no problem.
> 
> this is good - it would however not be at the EUR 600 / sq.mm level,it would be at double that, and also likely need Staf's paid-forassistance (if you're up for that, Staf?) to act as a firebreak forthe NDAs.

I don't subsidize the MPW runs I just charge the imec price to NLNet. I don't include normal industrial markup on the price for NLNet and just charge the (projected) time needed for the tape-out.
The cost is a little over the €600/mm² without packaging of the chips. For TSMC tape-out there is a minimum area charge of 25mm². For packaging you can go for semi-automatic packaging with a high cost per chip; prices are here. For high volume you have low per unit packaging cost (<$0.5/unit) but a start-up cost of over $5000.

greets,
Staf.


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Re: [libre-riscv-dev] daily kan-ban 07may2020 update

[Luke Kenneth Casson Leighton]

On Fri, May 8, 2020 at 12:02 PM Staf Verhaegen <staf@fibraservi.eu> wrote:

> I don't subsidize the MPW runs I just charge the imec price to NLNet. I don't include normal industrial markup on the price for NLNet and just charge the (projected) time needed for the tape-out.
> The cost is a little over the €600/mm² without packaging of the chips. For TSMC tape-out there is a minimum area charge of 25mm². For packaging you can go for semi-automatic packaging with a high cost per chip; prices are here. For high volume you have low per unit packaging cost (<$0.5/unit) but a start-up cost of over $5000.

appreciate the clarification, i assume the link was this
https://europractice-ic.com/wp-content/uploads/2020/05/General-MPW-EUROPRACTICE-200505-v8.pdf

l.

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