From: Yehowshua <yimmanuel3@gatech.edu>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] Fall 2022 Interfaces
Date: Thu, 11 Jun 2020 22:59:15 -0400
Message-ID: <E7F96DD9-4F42-4A32-B185-64279301CD5C@gatech.edu> (raw)
Was talking with Pine64 and Raptor about Fall2022 interfaces which I’m trying to finalize.
We can do everything including HDMI, ethernet, DDR4(via OpenCAPI OMI), and PCIE with SERDES lanes.
We need 10rx and 14tx SERDES.
4rx and 4tx for the OMI will need to run at 25GHz for DDR4 over OMI.
@Luke, is this possible for 45nm? Seems like it should be fine.
What type of expenses are we talking about for having Symbiotic EDA design the SERDES?
We’re going to need at least four different clock speeds - we will have to think about how to do this PLL wise - and down clock where possible.
https://libre-soc.org/45nm_Fall2022/?updated <https://libre-soc.org/45nm_Fall2022/?updated>
Yehowshua
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Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-12 2:59 Yehowshua [this message]
2020-06-12 3:00 ` Yehowshua
2020-06-12 4:01 ` Jacob Lifshay
2020-06-12 4:33 ` Cole Poirier
2020-06-12 5:46 ` Yehowshua
2020-06-12 7:07 ` Yehowshua
2020-06-12 11:03 ` Luke Kenneth Casson Leighton
2020-06-12 11:21 ` Luke Kenneth Casson Leighton
2020-06-12 12:38 ` Yehowshua
2020-06-12 13:30 ` Luke Kenneth Casson Leighton
2020-06-12 14:06 ` Hendrik Boom
2020-06-12 14:23 ` Cole Poirier
2020-06-12 19:34 ` Yehowshua
2020-06-12 19:43 ` Yehowshua
2020-06-12 21:42 ` Luke Kenneth Casson Leighton
2020-06-12 23:17 ` Jacob Lifshay
2020-06-13 0:10 ` Luke Kenneth Casson Leighton
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