[libre-riscv-dev] [Bug 155] a PLL is needed for the SoC

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=155

--- Comment #15 from Staf Verhaegen <staf@fibraservi.eu> ---
> Input: 24 MHz XTAL

AFAIK there is no crystal oscillator IP available for this project so I assumed
the input clock would be CMOS.

> So, regarding the specifications, the most important point determining the
> overall architecture is : 
> -- Jitter 

For a digital circuit jitter of the clock eats in the timing budget, the 
critical has to be fast enough to have result for the smallest clock cycle due
to jitter.
Analog/mixed-signal blocks will have their requirement on jitter, like
resolution/bandwidth for an ADC or error rate for SERDES.

-- 
You are receiving this mail because:
You are on the CC list for the bug.
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev