[libre-riscv-dev] [Bug 155] a PLL is needed for the SoC - bugzilla-daemon

From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 155] a PLL is needed for the SoC
Date: Tue, 26 May 2020 21:30:49 +0000
Message-ID: <bug-155-13-QucX3Xbmro@https.bugs.libre-soc.org/> (raw)
In-Reply-To: <bug-155-13@https.bugs.libre-soc.org/>

https://bugs.libre-soc.org/show_bug.cgi?id=155

--- Comment #16 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Staf Verhaegen from comment #15)
> > Input: 24 MHz XTAL
> 
> AFAIK there is no crystal oscillator IP available for this project so I
> assumed the input clock would be CMOS.

if we do not have all the pieces, yes we will use a CMOS external clock, this
is the fallback.

Professor Galyco, i may not have made it clear: we are not signing any NDAs and
so need *everything* from scratch that would normally be provided by the
Foundry (under NDA).  thank you for raising this, Staf.

did the PLL that you developed also include a XTAL interface?

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