[libre-riscv-dev] [Bug 155] a PLL is needed for the SoC

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=155

--- Comment #14 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Dimitri Galayko from comment #13)
> Dear all, I'm following the discussion by mail with Luke. There is a need to
> create a "open-source" and generic PLL with the following specifications: 
> 
> Technology: TSMC 180 nm
> Input: 24 MHz XTAL
> Output Frequency: ~300 MHz (~x12), with fractional intermediate frequencies
> x2, x3, x4, x5, x6.

as taps, this would be very helpful, so as to be able to do further
counter-dividers to create a wide frequency range for peripherals.

> A double of the frequency needs to be generated, in
> order to have a 300 MHz well-balanced 1 and 0 phases. 

interesting.  600mhz in 180nm.

> My first simulations in a 180 nm technology (not TSMC, but equivalent) shows
> that a 8 bits DCO may ensure a 600 MHz output frequency for all corners with
> a resolution able to provide a reasonably good jitter performance, with the
> power consumption of ~5mW.  

this sounds perfectly reasonable.

> So, regarding the specifications, the most important point determining the
> overall architecture is : 
> -- Jitter 
> -- power consumption. 
> 
> Is there any idea about what is expected for these two specifications ?

5mW is perfectly acceptable.  we do not have enough experience to say if jitter
is an issue, and for this first chip, being a noncritical test chip, if it is
unstable due to jitter we simply run tests at a slower speed, incrementally,
until it is.

-- 
You are receiving this mail because:
You are on the CC list for the bug.
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev