[libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=257

--- Comment #23 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
also, we're not doing an SMP core for the october 2020 deadline, because we are
only doing a single core.

therefore L1 and L2 SMP cache coherency is not needed.

we *need* to urgently get moving on this, we are seriously behind.

the fastest way to do that is to not spend months writing code that already
exists.

the fastest way to get the job done and meet that hard deadline is to only
spend days or weeks using existing code.

minerva *already* uses wishbone.

in addition, there is the "soc" code from enjoy-digital (litex) which has
testing infrastructure and connectivity to peripherals already done.

we *need* test infrastructure and peripheral connectivity.

we *cannot* spend weeks or months writing new test infrastructure that already
exists because we're using a completely new Bus Protocol (TileLink) that
completely isolates and cuts us off from that test infrastructure, because that
test infrastructure is all written to use Wishbone.

after the October 2020 deadline, when SMP cache coherency is a goal, we can
look at this again.

right now, we have to shelve SMP, and get the job done.  it's only six months
and at least two of those are going to be full-time working on the layout.

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