[libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=257

--- Comment #24 from Jacob Lifshay <programmerjake@gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #23)
> also, we're not doing an SMP core for the october 2020 deadline, because we
> are only doing a single core.
> 
> therefore L1 and L2 SMP cache coherency is not needed.

Ok, we can write the code to basically have whatever cache coherency stuff gets
written when getting the memory interface working and not worry about the L2 or
other cores existing at all, treating it as a writethrough transparent cache.
The design I'm working on is integrated closely enough with the L1 cache that
it will still need at least a little of the coherence protocol to support
atomics, but it can be built to have a WishBone interface adaptor.

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