[libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=257

--- Comment #21 from Jacob Lifshay <programmerjake@gmail.com> ---
Wishbone as-is is not sufficient for handling the interconnect between the L1
and L2 caches, or to any other device that can act as a bus master and is cache
coherent (such as other CPUs, OmniXtend, or cache coherent DMA). The reason is
because it has no concept of ownership of a particular cache block (or caching
at all), which is needed to support a cache coherence protocol.

Wishbone also has the drawback of memory bandwidth being limited by the bus
having a max width of 64 bits (ends up as 6.4GB/s peak theoretical bandwidth at
800MHz), we are likely to want more bandwidth between cores and the L2 cache.

Minerva's memory interface appears to not be designed to handle cache coherence
at all, so would need to be redesigned to support that if we wanted to use
Minerva's memory interface, which I don't think we should since we would need
to rewrite the majority of Minerva's memory interface code.

Using wishbone for devices that don't need to be cache coherent and don't need
large memory bandwidth (less than 1GB/s or so) is still a good idea.

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