[libre-riscv-dev] [Bug 287] New: corrections to commit f17100d6c435aec47b17acb188272a7e9b3cf67d

[libre-riscv-dev] [Bug 287] New: corrections to commit f17100d6c435aec47b17acb188272a7e9b3cf67d

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=287

            Bug ID: 287
           Summary: corrections to commit
                    f17100d6c435aec47b17acb188272a7e9b3cf67d
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl@lkcl.net
          Reporter: lkcl@lkcl.net
                CC: libre-riscv-dev@lists.libre-riscv.org
   NLnet milestone: ---

* add suitable separate unit tests for both mul and carry.
  add them as *separate commits* with a message "unit test for sim multiply"
  and "unit tests for sim carry"

* remove the whitespace added around lines 140.  ensure that there is
  only one newline (not two)

* remove the redundant brackets in these two statements:

+        if(cry_out==1):
+            if(result > 0xFFFFFFFF):

* ensure that one space is between "if" and its "test"

   if cry_out == 1:

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[libre-riscv-dev] [Bug 287] corrections to commit f17100d6c435aec47b17acb188272a7e9b3cf67d

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=287

Luke Kenneth Casson Leighton <lkcl@lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Assignee|lkcl@lkcl.net               |libre-soc@platen-software.d
                   |                            |e

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[libre-riscv-dev] [Bug 287] corrections to commit f17100d6c435aec47b17acb188272a7e9b3cf67d

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=287

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
tobias, see:
http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-April/006019.html

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