[libre-riscv-dev] [Bug 288] intro post for powerpc-notebook.org and https://www.powerprogress.org/en/

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=288

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Yehowshua from comment #3)
> Ah I see. That makes sense to me.
> 
> So this:
> 
> LibreSOC is an Open Hardware and Open Software project that aims to deliver
> a physical  POWER compliant SOC that comes complete with a CPU, GPU, VPU,
> and DDR controller. All the software and hardware from the drivers down to
> the RTL and VLSI cells are open. 

libre-licensed.  "open" leaves the possibility of accusations of "fake open
source".

"we'll release the code when it's revision 1.0... but it's open!".

"we'll release the code when it's ready... but it's open!"

"we'll release the code... under a non-commercial license... but it's open!"

> LibreSOC is also providing the necessary
> drivers amongst which include Vulkan and OpenCL drivers.

no, not OpenCL.  that has to come later as we'll need an entire new
grant to do it.

> The intended market includes customers who desire acceleration in the
> embedded space without relying on ARM's proprietary drivers that have been
> know to break in the past.

and piss people off :)

> The first iteration of LibreSOC targets a single-core at 180nm. Subsequent
> generations target more cores at a smaller node size.

looks good.  i'd put "target multiple SMP cores" though.  "more cores"
could mean "NUMA" or "SIMT".  SIMT is almost impossible to program for
general-purpose, and NUMA is a royal pain, memory-wise.

-- 
You are receiving this mail because:
You are on the CC list for the bug.
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev