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From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 288] intro post for powerpc-notebook.org and https://www.powerprogress.org/en/
Date: Wed, 22 Apr 2020 16:16:38 +0000
Message-ID: <bug-288-13-yhAEre9Qjl@https.bugs.libre-soc.org/> (raw)
In-Reply-To: <bug-288-13@https.bugs.libre-soc.org/>

https://bugs.libre-soc.org/show_bug.cgi?id=288

Jacob Lifshay <programmerjake@gmail.com> changed:

           What    |Removed                     |Added
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                 CC|                            |programmerjake@gmail.com

--- Comment #5 from Jacob Lifshay <programmerjake@gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #4)
> > The first iteration of LibreSOC targets a single-core at 180nm. Subsequent
> > generations target more cores at a smaller node size.
> 
> looks good.  i'd put "target multiple SMP cores" though.  "more cores"
> could mean "NUMA" or "SIMT".  SIMT is almost impossible to program for
> general-purpose, and NUMA is a royal pain, memory-wise.

Sounds good, though, it would be NUMA if we have multiple chips wired together
using OmniXpress or similar.


Also, we should be consistent spelling Libre-SOC with the hyphen like we
agreed.

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  parent reply index

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-19 19:29 [libre-riscv-dev] [Bug 288] New: " bugzilla-daemon
2020-04-22 12:26 ` [libre-riscv-dev] [Bug 288] " bugzilla-daemon
2020-04-22 12:49 ` bugzilla-daemon
2020-04-22 15:41 ` bugzilla-daemon
2020-04-22 16:00 ` bugzilla-daemon
2020-04-22 16:16 ` bugzilla-daemon [this message]
2020-04-22 19:00 ` bugzilla-daemon
2020-04-22 19:14 ` bugzilla-daemon
2020-04-22 19:42 ` bugzilla-daemon

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