[libre-riscv-dev] [Bug 304] New: Define minimum viable interface set for 180nm ASIC

[libre-riscv-dev] [Bug 304] New: Define minimum viable interface set for 180nm ASIC

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=304

            Bug ID: 304
           Summary: Define minimum viable interface set for 180nm ASIC
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl@lkcl.net
          Reporter: lkcl@lkcl.net
                CC: libre-riscv-dev@lists.libre-riscv.org
   NLnet milestone: ---

define and document, at https://libre-soc.org/180nm_Oct2020/interfaces/
a set of interfaces for a minimum viable 180nm ASIC

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[libre-riscv-dev] [Bug 304] Define minimum viable interface set for 180nm ASIC

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=304

Yehowshua <yimmanuel3@gatech.edu> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |yimmanuel3@gatech.edu
                URL|                            |http://lists.libre-riscv.or
                   |                            |g/pipermail/libre-riscv-dev
                   |                            |/2020-May/006374.html

--- Comment #1 from Yehowshua <yimmanuel3@gatech.edu> ---
Oh, my bad I'm just now seeing this.

Relea

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[libre-riscv-dev] [Bug 304] Define minimum viable interface set for 180nm ASIC

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=304

Yehowshua <yimmanuel3@gatech.edu> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                URL|http://lists.libre-riscv.or |
                   |g/pipermail/libre-riscv-dev |
                   |/2020-May/006374.html       |

--- Comment #2 from Yehowshua <yimmanuel3@gatech.edu> ---
Relevant Links:

http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006374.html
http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006372.html
https://libre-soc.org/shakti/m_class/pinouts/
https://gitlab.raptorengineering.com/raptor-engineering-public/lpc-spi-bridge-fpga/tree/master

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[libre-riscv-dev] [Bug 304] Define minimum viable interface set for 180nm ASIC

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=304

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
*** Bug 303 has been marked as a duplicate of this bug. ***

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[libre-riscv-dev] [Bug 304] Define minimum viable interface set for 180nm ASIC

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=304

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
yehowshua i added a stub/starting-point ls180

https://git.libre-soc.org/?p=pinmux.git;a=blob;f=src/spec/ls180.py;h=77c5f1f7f7923cb8292499bac189ff1ce8f3b6ff;hb=aca6d68a6159136fe1f36c6430e2ffd07da13e8c

also added a stub / dummy LPC function:
https://git.libre-soc.org/?p=pinmux.git;a=blob;f=src/spec/pinfunctions.py;h=e46be8d114f00bbf571092c4e7a9ec5ece39d04b;hb=aca6d68a6159136fe1f36c6430e2ffd07da13e8c#l52

it will need its pin naming correcting, and also in ls180.py everything
including LPC moving to a single column.

we need to move quickly on this because Rudi is waiting for us
to communicate back to him the required peripheral set, and he
is experienced enough to know that we are well beyond the industry
standard time for making these decisions.

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[libre-riscv-dev] [Bug 304] Define minimum viable interface set for 180nm ASIC

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=304

--- Comment #5 from Yehowshua <yimmanuel3@gatech.edu> ---
OK. I'll try and have it finished by Thursday afternoon.

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[libre-riscv-dev] [Bug 304] Define minimum viable interface set for 180nm ASIC

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=304

--- Comment #6 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
conversation notes from Tim (Raptor Engineering)

priority:

* 2x SPI master
* 4x I2C master
* 2x UART
* 4x LPC master
* EINT* Serialsed IRQ (LPC, from PCIe) - 15 or so IRQs, these are
PC>PCIe>OpenPower mappings

Quad SPI raptorengineering
LPC bridge github raptorengineering
~

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