[libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=313

--- Comment #15 from Michael Nolan <mtnolan2640@gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #14)
> waaaa...
> 
>     insn       CR  SPR1  SPR2    SPR3
>     ----       --  ----  ----    ----
>     op_b       xx  LR     xx     xx
>     op_ba      xx  LR     xx     xx
>     op_bl      xx  LR     xx     xx
>     op_bla     xx  LR     xx     xx
>     op_bc      CR, LR,    CTR    xx
>     op_bca     CR, LR,    CTR    xx
>     op_bcl     CR, LR,    CTR    xx
>     op_bcla    CR, LR,    CTR    xx
>     op_bclr    CR, LR,    CTR    xx
>     op_bclrl   CR, LR,    CTR    xx
>     op_bcctr   CR, LR,    CTR    xx
>     op_bcctrl  CR, LR,    CTR    xx
>     op_bctar   CR, LR,    CTR,   TAR
>     op_bctarl  CR, LR,    CTR,   TAR
> 
>     op_sc      xx  xx     xx     MSR
>     op_scv     xx  LR,    SRR1,  MSR
>     op_rfscv   xx  LR,    CTR,   MSR
>     op_rfid    xx  SRR0,  SRR1,  MSR
>     op_hrfid   xx  HSRR0, HSRR1, MSR
> 
> and if we did TRAP in the Branch pipeline as well, that would be
> *six* incoming 64-bit register latch paths.  nooo, i don't think so :)


That table is a bit large, at least for the branch instructions. None of the
branches except for bclr(l) need to read LR, only write to it. And bclr doesn't
need to read TAR, so multiplexing TAR/LR on the same port would be possible. 

> so the above table should guide the numbering.  LR - that's not an SPR,
> is it? 
It is, it's SPR #8


what are the opcodes starting with op_sc? I don't see any of them in the
power_enums list, nor do I see corresponding opcodes in the power ISA
specification

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