From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG
Date: Thu, 21 May 2020 17:23:27 +0000
Message-ID: <bug-333-13-A81mRuzcox@https.bugs.libre-soc.org/> (raw)
In-Reply-To: <bug-333-13@https.bugs.libre-soc.org/>
https://bugs.libre-soc.org/show_bug.cgi?id=333
--- Comment #11 from Michael Nolan <mtnolan2640@gmail.com> ---
Luke, there's not a way to do something like a C union in nmigen is there? I'm
thinking for the CR pipeline to have it put one or two of the crs in the 32 bit
cr input for the cases where it doesn't need the full cr as input.
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Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-20 17:55 [libre-riscv-dev] [Bug 333] New: " bugzilla-daemon
2020-05-20 18:16 ` [libre-riscv-dev] [Bug 333] " bugzilla-daemon
2020-05-20 18:37 ` bugzilla-daemon
2020-05-20 18:45 ` bugzilla-daemon
2020-05-20 18:52 ` bugzilla-daemon
2020-05-20 18:59 ` bugzilla-daemon
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2020-05-20 19:39 ` bugzilla-daemon
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2020-05-21 2:05 ` bugzilla-daemon
2020-05-21 16:02 ` bugzilla-daemon
2020-05-21 17:23 ` bugzilla-daemon [this message]
2020-05-21 17:32 ` bugzilla-daemon
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2020-05-22 13:36 ` bugzilla-daemon
2020-05-22 13:49 ` bugzilla-daemon
2020-05-24 20:48 ` bugzilla-daemon
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