From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG
Date: Thu, 21 May 2020 17:39:24 +0000
Message-ID: <bug-333-13-qjxD0xuAXR@https.bugs.libre-soc.org/> (raw)
In-Reply-To: <bug-333-13@https.bugs.libre-soc.org/>
https://bugs.libre-soc.org/show_bug.cgi?id=333
--- Comment #13 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #12)
> however the (planned) cyclic buffers now become even more complex, because
> each register could contain two values not one.
answer: it would not be a good idea. much simpler - cleaner - to have extra 4
bit data path(s) for the src CR regs that won't go into src1.
remember, it would mean that *at the regfile* access to a *pair* of 4 bit Read
Ports would need to be synchronised, just to make the transfer of 2
simultaneous 4 bit values down that one 32 bit path.
this in addition to making the cyclic buffers far more complex.
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Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-20 17:55 [libre-riscv-dev] [Bug 333] New: " bugzilla-daemon
2020-05-20 18:16 ` [libre-riscv-dev] [Bug 333] " bugzilla-daemon
2020-05-20 18:37 ` bugzilla-daemon
2020-05-20 18:45 ` bugzilla-daemon
2020-05-20 18:52 ` bugzilla-daemon
2020-05-20 18:59 ` bugzilla-daemon
2020-05-20 18:59 ` bugzilla-daemon
2020-05-20 19:39 ` bugzilla-daemon
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2020-05-20 19:46 ` bugzilla-daemon
2020-05-21 2:05 ` bugzilla-daemon
2020-05-21 16:02 ` bugzilla-daemon
2020-05-21 17:23 ` bugzilla-daemon
2020-05-21 17:32 ` bugzilla-daemon
2020-05-21 17:39 ` bugzilla-daemon [this message]
2020-05-21 17:46 ` bugzilla-daemon
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2020-05-21 19:59 ` bugzilla-daemon
2020-05-22 13:36 ` bugzilla-daemon
2020-05-22 13:49 ` bugzilla-daemon
2020-05-24 20:48 ` bugzilla-daemon
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