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From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 350] LDSTCompUnit also needs to support zeroing on RA
Date: Mon, 25 May 2020 11:46:13 +0000
Message-ID: <bug-350-13-3XQ5eg3MH6@https.bugs.libre-soc.org/> (raw)
In-Reply-To: <bug-350-13@https.bugs.libre-soc.org/>

https://bugs.libre-soc.org/show_bug.cgi?id=350

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #1)
> added, untested, however may have a block when both zero and immediate set.

it's fine.  unit test modified as follows:

+    rd = 0b00
+    if not imm_ok:
+        rd |= 0b10
+    if not zero_a:
+        rd |= 0b01
+
+    if rd:
+        yield dut.rd.go.eq(rd)
+        yield from wait_for(dut.rd.rel)
+        yield dut.rd.go.eq(0)

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  parent reply index

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-25  0:13 [libre-riscv-dev] [Bug 350] New: " bugzilla-daemon
2020-05-25  0:14 ` [libre-riscv-dev] [Bug 350] " bugzilla-daemon
2020-05-25  0:14 ` bugzilla-daemon
2020-05-25  4:03 ` bugzilla-daemon
2020-05-25 11:46 ` bugzilla-daemon [this message]
2020-05-25 11:57 ` bugzilla-daemon
2020-05-28 10:44 ` bugzilla-daemon

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