[libre-riscv-dev] [Bug 350] LDSTCompUnit also needs to support zeroing on RA

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=350

Luke Kenneth Casson Leighton <lkcl@lkcl.net> changed:

           What    |Removed                     |Added
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           Assignee|lkcl@lkcl.net               |cestrauss@gmail.com

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
cesar this one likewise needs similar tests to the MultiCompUnit, might even
be able to share the same base classes at some point.

again it needs that "multi-process" simulation model:

* one function doing setup, setting oper_i, issue_i, then monitoring busy_o
  before exiting

* another that checks busy_o and, when set, proceeds to monitor a single
  bit of rd.req, sets the corresponding bit of rd.go for one cycle, then
  monitors busy_o before exiting

* likewise for write requests.

this is exactly the same as needed for MultiCompUnit (up to this point).
the additions obviously are to have extra functions that:

* monitor req_adr_o and set go_adr_i
* monitor req_st_o and set go_st_i
* check the address and the data afterwards

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