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From: whygee@f-cpu.org
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] morphing 6600 code to use power decoder
Date: Thu, 09 Apr 2020 02:47:08 +0200
Message-ID: <393761a54bdab5a0ca52e05bbdedf330@f-cpu.org> (raw)
In-Reply-To: <CAPweEDwDNnrpq=F2=r3i+XsXveheC23fzebRZVTAkL8eejaC+w@mail.gmail.com>

On 2020-04-08 15:26, Luke Kenneth Casson Leighton wrote:
> however one key difference will be that whilst immediates are read from 
> the
> opcode, registers are *not* immediately read from the regfile, they are
> done by way of a regfile port bus, and only when available are 
> "latched"
> into registers.
> 
> only when all read regs become available can the op proceed.
> 
> so it is a little different from microwatt which just does, in 
> sequence,
> decode read execute write.
> 
> it should be fine.
> 
> l.

Could you please elaborate on your system ?
Is there some sort of buffer to store the immediates
while waiting for other operands to be ready ?

yg

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Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-08 13:26 Luke Kenneth Casson Leighton
2020-04-09  0:47 ` whygee [this message]
2020-04-09  1:21   ` Luke Kenneth Casson Leighton
2020-04-10 15:01     ` Luke Kenneth Casson Leighton
2020-04-11 11:20       ` Luke Kenneth Casson Leighton
2020-04-12 12:32         ` Luke Kenneth Casson Leighton
2020-04-13 14:16           ` Luke Kenneth Casson Leighton
2020-04-13 17:46             ` whygee
2020-04-13 18:27               ` Luke Kenneth Casson Leighton
2020-04-14 19:12                 ` Luke Kenneth Casson Leighton
2020-04-16 12:19                   ` Luke Kenneth Casson Leighton
2020-04-16 15:41                     ` Luke Kenneth Casson Leighton
2020-04-18 11:06                       ` Luke Kenneth Casson Leighton
2020-04-23 17:16                         ` Luke Kenneth Casson Leighton
2020-04-24 20:11                           ` Luke Kenneth Casson Leighton

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