Re: [libre-riscv-dev] morphing 6600 code to use power decoder

From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] morphing 6600 code to use power decoder
Date: Fri, 24 Apr 2020 21:11:27 +0100
Message-ID: <CAPweEDzpNTUPW4P+wgDatSv91mddXO+_e_EYRECJOKjhPVqHPw@mail.gmail.com> (raw)
In-Reply-To: <CAPweEDy5CCRESLD7-rT9e3pHMP8kEUQW0KpRGGwkyw=ZS6Vdkw@mail.gmail.com>

i started on adding LD/ST back in: and, argh, i spotted that the
LDSTCompUnit needs some rework / redesign.  it "worked" previously
however there were some assumptions which, because of the new
multi-signalling, don't work.

i think i will take the opportunity to remove the triple-functionality
from the LDSTCompUnit.  the original intention was to have its ADD ALU
be capable of performing standard ADD arithmetic, thus allowing us to
have dozens of parallel ADD units.

we're running out of time, and unfortunately i'm not coping with the
logic complexity involved in writing out these state-based diagrams
(last time it took 3 weeks to get right), so i'm going to cut ADD and
simply make the address-generation part of the actual LDSTCompUnit.

l.

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