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From: Yehowshua <yimmanuel3@gatech.edu>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] daily kan-ban update 19jul2020
Date: Sun, 19 Jul 2020 18:46:00 -0400
Message-ID: <AF38DB3D-DCBC-42D7-A75A-1AC767AA7FB1@gatech.edu> (raw)
In-Reply-To: <CAPweEDyY=RG6WXDiVQNFz7Q+o0zNDDp5LdSR0hKPUVH-FE9Seg@mail.gmail.com>

> 
> in our case that's 17,000 flattened signals.


Well, oMigen won’t flatten out verilog black boxes, but it
will flatten out the dram controller for example.

Which hopefully you don’t need to debug…

Verilator retains the hierarchy of whatever it consumes.
SO you’ll get a hierarchical CPU and flat peripherals.


Yehowshua
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Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-19 21:36 Luke Kenneth Casson Leighton
2020-07-19 21:38 ` Yehowshua
2020-07-19 22:21   ` Luke Kenneth Casson Leighton
2020-07-19 22:46     ` Yehowshua [this message]
2020-07-19 23:19       ` Luke Kenneth Casson Leighton

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