From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] daily kan-ban update 19jul2020
Date: Sun, 19 Jul 2020 23:21:51 +0100
Message-ID: <CAPweEDyY=RG6WXDiVQNFz7Q+o0zNDDp5LdSR0hKPUVH-FE9Seg@mail.gmail.com> (raw)
In-Reply-To: <20B7B259-F2C5-4B0D-BBE7-5DDF0C09EE96@gatech.edu>
On Sunday, July 19, 2020, Yehowshua <yimmanuel3@gatech.edu> wrote:
> > i have no idea if verilator generates vcd files which would allow
> debugging
> > if there are issues (instructions missing for example)
>
> Verilator does generate VCDs…
> LiteX abstracts that away for you, however,
> I will say that its a pretty painful process
> to run through LiteX generated VCds.
>
> They are flattened as oMigen outputs flat verilog
niice.
in our case that's 17,000 flattened signals.
l.
--
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Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-19 21:36 Luke Kenneth Casson Leighton
2020-07-19 21:38 ` Yehowshua
2020-07-19 22:21 ` Luke Kenneth Casson Leighton [this message]
2020-07-19 22:46 ` Yehowshua
2020-07-19 23:19 ` Luke Kenneth Casson Leighton
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