From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] daily kan-ban update 19jul2020
Date: Mon, 20 Jul 2020 00:19:17 +0100
Message-ID: <CAPweEDx+EveurF8jTtCmkyMksFipLcwpSFDaM3Nr+PnLg+jtqw@mail.gmail.com> (raw)
In-Reply-To: <AF38DB3D-DCBC-42D7-A75A-1AC767AA7FB1@gatech.edu>
On Sunday, July 19, 2020, Yehowshua <yimmanuel3@gatech.edu> wrote:
> >
> > in our case that's 17,000 flattened signals.
>
> Verilator retains the hierarchy of whatever it consumes.
> SO you’ll get a hierarchical CPU and flat peripherals.
thank goodness for that.
many of the pipeline signals have not been given globally unique names,
meaning there's dozens of duplicate "ready_o" etc. and more.
l.
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Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-19 21:36 Luke Kenneth Casson Leighton
2020-07-19 21:38 ` Yehowshua
2020-07-19 22:21 ` Luke Kenneth Casson Leighton
2020-07-19 22:46 ` Yehowshua
2020-07-19 23:19 ` Luke Kenneth Casson Leighton [this message]
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