[libre-riscv-dev] daily kan-ban update 19jul2020

From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] daily kan-ban update 19jul2020
Date: Sun, 19 Jul 2020 22:36:08 +0100
Message-ID: <CAPweEDzXUd4dzzEFf1g3ud00rUx_6a_pXngQRouqQFh+-WZizw@mail.gmail.com> (raw)

yesterday:

* got alu FSM working example with a CompUnit "manager"

today:

* walked through some examples using cxxsim and encountered some bugs,
under investigation.
* talked with florent from enjoy-digital, he is going to add libre-soc
test_issuer to litex upstream for us.

once compiling test_issuer to run under verilator is possible, we *should*
be able to put together a 16550 uart example from fusesoc pretty quickly.

that will allow running of the full microwatt hello_world binary and, as
long as we can get access to the serial console we will have a first
"proper" demo.

from there running the microwatt micropython binary should also be easy.

i have no idea if verilator generates vcd files which would allow debugging
if there are issues (instructions missing for example)

l.

-- 
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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